Manufacturing method of grid
A manufacturing method and gate technology, applied in the field of gate manufacturing, can solve problems affecting component electrical properties, polysilicon gate damage, photoresist transition loss, etc.
Active Publication Date: 2021-04-13
SHANGHAI HUALI INTEGRATED CIRCUIT CORP
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Problems solved by technology
The transition loss of the photoresist caused by the excessive height difference of the gate is easy to cause damage to the active region and the polysilicon gate, which will affect the electrical properties of the component.
Method used
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[0024] The technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0025] In one embodiment of the present invention, a method for manufacturing a gate is provided, which can be referred to figure 2 , figure 2 It is a flowchart of a manufacturing method of a gate according to an embodiment of the present invention. The gate manufacturing method provided by the present invention includes: S1: providing a semiconductor substrate, and sequentially forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate; S2: forming a hard mask on the s...
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The invention relates to a method for manufacturing a grid, and relates to a method for manufacturing a semiconductor integrated circuit. In the manufacturing process of the grid, a contact hole etching stop layer and an interlayer film are formed. First, the contact hole etching stop layer with the highest height is used as the stop layer Perform chemical mechanical polishing on the interlayer film and achieve the first planarization; then perform a dry etching process to remove the oxide layer on the gate to achieve the second planarization, and over-etch the interlayer film downward until the interlayer film is opened At least one hole in the gate, and then fill the interlayer film composed of the oxide layer, then the interlayer film will completely fill the gaps and holes between the gates and extend to the top of the gate, and then use the polysilicon gate as a stop layer The third planarization process improves the consistency of the gate height, improves the hole problem, and does not damage the structure of the source and drain, thereby improving chip performance.
Description
technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a gate. Background technique [0002] In the existing advanced logic chip technology, components usually include n-type field effect transistors (FETs), namely nFETs, and p-type field effect transistors, namely pFETs. In the existing method, a dummy polysilicon (dummy poly) process is used to prepare a temporary polysilicon gate to define the source / drain, and then the dummy polysilicon gate is removed, and a metal gate (MG) is formed in the area where the polysilicon gate is removed. [0003] In addition, in order to increase the electrical performance of the components, an additional component enhancement process will be performed in addition to the pFET or nFET process. The component enhancement process will directly affect the height of the gate between different subsequent components, resulting in the difference in g...
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IPC IPC(8): H01L21/8238H01L21/28
Inventor 陈小强李镇全
Owner SHANGHAI HUALI INTEGRATED CIRCUIT CORP