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Interrupt processing method and interrupt processing device

A processing method and central processing unit technology, applied in the computer field, can solve problems such as incompatibility of byte order of interrupt messages, and achieve the effect of ensuring correct triggering

Active Publication Date: 2019-07-05
ZTE CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] In order to solve the above technical problems, the present application provides an interrupt processing method and an interrupt processing device, which can solve the problem of incompatibility of byte order of interrupt messages

Method used

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  • Interrupt processing method and interrupt processing device
  • Interrupt processing method and interrupt processing device
  • Interrupt processing method and interrupt processing device

Examples

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no. 1 example

[0079] In the first embodiment, a hardware breakpoint is used to adjust the MSI / MSI-X interrupt message. Hardware breakpoints are a debugging mechanism provided by the central processing unit, which can generate exceptions when specific memory addresses are modified. In the first embodiment, hardware breakpoints are used to monitor MSI / MSI-X interrupt messages.

[0080] In the first embodiment, when the PCIE device driver is initialized, the configuration of the Message Address register is modified so that it points to the memory address monitored by the hardware breakpoint, that is, the preprocessing address. In this way, the MSI / MSI-X interrupt message reported by the PCIE device will trigger a hardware breakpoint exception; and in the process of hardware breakpoint exception handling, through the exception handling function set in advance, it can write to the corresponding address of the preprocessing address. The value of the memory is written to the MSIIR register after ...

no. 2 example

[0086] In the second embodiment, the PCIE error detection interrupt of the central processing unit is used to quickly respond to the adjustment of the MSI / MSI-X interrupt message.

[0087] Taking the PCIE controller in the processor produced by NXP (formerly Freescale Semiconductor) as an example, whether it is a PowerPC processor or a QorIQ Layerscape processor based on the ARM architecture, it will provide a PCIE error detection mechanism other than the PCIE standard. That is, when an error occurs on the PCIE bus, an interrupt can be generated to notify the central processing unit, and the information of the message causing the error can be recorded. For example: for memory read and write transactions on the PCIE bus, if the target PCIE bus address of the access is not used, that is, no device responds to the read and write request, then PCI interconnection without mapping (PCI Express) will occur. no map) error, then report the PCIE error interrupt to the central processing...

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Abstract

The invention discloses an interrupt processing method and an interrupt processing device, and the method comprises the steps: carrying out the byte sequence adjustment of the value of hardware corresponding to a write-in preprocessing address through a central processing unit, and enabling a slave device to be compatible with the byte sequence of the central processing unit; and the central processing unit writes the value subjected to byte order adjustment into an MSI mechanism register to trigger interruption; wherein the preprocessing address is a PCIE bus address; and preprocessing hardware corresponding to the address to check that the hardware is modified, and calling a software mode to adjust the byte sequence. According to the invention, the target address configured in the information address register is replaced by the special address; according to the interrupt processing method and device, the preprocessing process for the current interrupt is ingeniously generated, in thepreprocessing process, the problem that interrupt message word node sequences are incompatible is simply adjusted in a software processing mode, it is guaranteed that slave equipment and a central processing unit are compatible in byte sequences, and therefore correct triggering of the interrupt is guaranteed.

Description

technical field [0001] The present application relates to but not limited to computer technology, especially to an interrupt processing method and an interrupt processing device. Background technique [0002] Peripheral Component Interconnect Express (PCIE, Peripheral Component Interconnect Express) bus is a high-speed serial bus widely used in computer systems for connecting central processing units (CPU, Central Processing Unit) and other high-performance chips such as network cards, graphics cards, Ethernet switch chip, etc. The PCIE controller contained on the side of the central processing unit is a master controller, and the PCIE device outside the central processing unit is a slave device. [0003] The PCIE standard defines three types of transactions for data transmission, namely: memory read and write transactions, input / output (I / O) read and write transactions, and configuration space read and write transactions. Among them, I / O read and write transactions are ou...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/42G06F13/24
CPCG06F13/4282G06F13/24G06F2213/0026G06F13/42Y02D10/00
Inventor 徐阳
Owner ZTE CORP
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