Chip packaging structure and packaging method thereof

Abstract

The invention discloses a chip packaging structure and a packaging method thereof, comprising: a plurality of bare chips, one side of which is provided with a plurality of connection posts; The surface of the connection column away from the bare chip side; the redistribution layer, the redistribution layer is located on the side away from the connection column from the bare chip, and the redistribution layer is electrically connected to the connection column; the solder ball group, the solder ball group is located on the redistribution layer away from the bare chip One side of the chip, and the solder ball group includes a plurality of first solder balls, the first solder balls are electrically connected to the redistribution layer; and at least one electronic component, the electronic component is arranged on the side of the encapsulation layer close to the solder ball group ; Along the direction perpendicular to the plane where the bare chip is located, the orthographic projection of the electronic component is located between the orthographic projections of two adjacent bare chips. Compared with the prior art, the integration degree of the packaging structure can be effectively improved, which is beneficial to the miniaturization development of electronic products.

Description

technical field [0001] The present invention relates to the technical field of packaging, and more particularly, to a chip packaging structure and a packaging method thereof. Background technique [0002] With the continuous development of integrated circuit technology, electronic products tend to develop in the direction of miniaturization, intelligence and high reliability, which requires higher and higher integration of circuits in electronic products. The current packaging technology is generally aimed at the packaging of a single chip. The packaged chip needs to be assembled on a PCB board (Printed circuit board, printed circuit board), and other components are connected through the circuit on the PCB board to realize its function. But there are the following problems: [0003] 1) The components and packaged chips need to be assembled on the PCB board respectively, the assembly process is complicated, and when the component size is small, the assembly is difficult, and...

AI Technical Summary

Problems solved by technology

[0003] 1) Components and packaged chips need to be assembled on the PCB respectively, the assembly process is complex, and when the size of the components is small, the assembly is difficult, and it is difficult to ensure the reliability of the connection with the circuit on the PCB; When the size is large, it will occupy a large space on the PCB board, which is not conducive to the further miniaturization of electronic products;

[0004] 2) In order to connect to the components through the circuit on the PCB board, additional corresponding pins need to be set on the packaged chip, so that the number of pins on the packaged chip is large. The gap between the pins is also relatively small, and it is very easy to cause a short circuit between the pins due to the low precision of the assembly process, which affects the normal use of the packaged chip

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