Configurable register and data access method based on same

Abstract

The invention provides a configurable register and a data access method based on the configurable register. The configurable register comprises a register file, a plurality of configurable ports and adiscrete address cache register, wherein the register file comprises a plurality of vector data registers for storing the vector data to be accessed and a decoder for decoding an externally inputtedcontrol instruction to execute the control instruction, the configurable port comprises a plurality of read ports and a plurality of write ports and is used for configuring the preset parameters according to the first address configuration information in the control instruction, generating a first data access address and caching the first data access address, obtaining the second address configuration information from the discrete address cache register, calculating a second data access address, and reading / writing the corresponding discrete data into the register file according to the seconddata access address, and the discrete address cache register comprises at least one read address register and at least one write address register and is used for caching the second address configuration information in the control instruction.

Description

technical field [0001] The invention relates to the field of processors, in particular to a configurable register and a data access method based on the configurable register. Background technique [0002] Matrix, vector, and transformation operations in digital signal algorithms have occupied a very core position. The heterogeneous multi-core vector processor is optimized from the DSP (Digital Signal Processor, digital signal processor) instruction system and architecture. , a processor for array signal processing, which has many characteristics similar to DSP. Because it is often processed for high-intensity data, and the processing speed is fast, the data access address changes frequently, and the address calculation needs to be independent of the data operation processing to reduce the pressure on the operation unit. Therefore, it is necessary to design a high-performance address generation unit to realize signal processing and address calculation in parallel, so as to i...

AI Technical Summary

Problems solved by technology

[0003] Although the existing address generation components can support access to vector addresses, for reading and writing regular source data, it is still necessary to read / write data through a fixed index method, which will not only cause excessive number of Instructions will bring a burden to programmers, and will also affect the instruction access of DSP and affect the calculation efficiency. It is also impossible to provide efficient support for discrete address access with a relatively fixed pattern, causing a lot of inconvenience to the data processing process.

Images