Unlock instant, AI-driven research and patent intelligence for your innovation.

Fast boot systems and methods for programmable logic devices

A technology for programming logic and devices, which is applied in the field of programmable logic devices and can solve the problem that configuration data takes a considerable amount of time.

Pending Publication Date: 2019-07-16
LATTICE SEMICON CORP
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Loading configuration data can take a considerable amount of time

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Fast boot systems and methods for programmable logic devices
  • Fast boot systems and methods for programmable logic devices
  • Fast boot systems and methods for programmable logic devices

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] Various techniques for facilitating fast startup for PLDs are provided. In some embodiments, a PLD may be implemented with a fast boot capability that allows at least a portion of the PLD's input / output (I / O) structure to provide I / O functionality. Fast start-up may also be referred to as fast wake-up, fast activation, early start-up, early wake-up, early activation, or variations thereof. In some cases, alternatively or additionally, a portion of the logic structure and / or other components of the PLD may be designated for fast startup. To this end, a certain function of the PLD (eg, I / O and / or logic functions) can be designated for fast startup.

[0034] In one embodiment, to facilitate fast boot, configuration data associated with a portion of an I / O structure designated for fast boot may be loaded into a configuration memory unit associated with that portion of the I / O structure. Once a configuration memory cell has been configured (e.g., programmed, loaded with co...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present disclosure relates to a fast boot system and a method for a programmable logic device, and in particular to a Programmable Logic Device (PLD), a corresponding method, a non-transitory machine-readable storage medium comprising instructions, and a corresponding system. Various techniques are provided for implementing fast boot of a Programmable Logic Device (PLD). In an example, a method includes: configuration data associated with the PLD is received. The PLD includes: an array of memory cells is configured, including logical block memory cells and input / output (I / O) block memory cells associated with a logical structure and an I / O structure, respectively, of the PLD. The method further comprises the following steps: programming a subset of the I / O block memory cells with the configuration data; and providing a wake-up signal for activating a function associated with a portion of the I / O fabric. The method further comprises the following steps: the remaining configuration memory cells in the array are programmed with configuration data, wherein the remaining configuration memory cells comprise at least a subset of the logic block memory cells.

Description

[0001] Cross References to Related Applications [0002] This patent application claims priority and benefit to U.S. Provisional Patent Application 62 / 612,265, filed December 29, 2017, the entire contents of which are incorporated herein by reference. technical field [0003] The present invention relates generally to programmable logic devices, and more particularly to fast-start techniques for such devices. Background technique [0004] Programmable logic devices (PLDs) such as Field Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices (CPLDs), Field Programmable System-on-Chip (FPSC ), or other types of programmable devices). Typically, user designs are synthesized and mapped into configurable resources including, by way of non-limiting example: programmable logic gates, look-up tables (LUTs), embedded hardware, interconnects, and / or in specific PLD Other types of resources available in . The physical layout and routing for the synthesized and mapped u...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/4401G06F9/445
CPCG06F9/4418G06F9/44505H03K19/17756H03K19/17758G06F3/0611G06F3/0632G06F3/0673G06F21/575G06F2221/033
Inventor F·张G·汉兹S·辛格W·韩R·拉尔J·科普伦S·赫加德M·H·丁
Owner LATTICE SEMICON CORP