A kind of double split gate power mosfet device and its preparation method
A double-split and device technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as unrealizable and improved breakdown voltage, and achieve improved production efficiency, improved breakdown voltage, and withstand voltage capability Improved effect
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Embodiment 1
[0043] A specific embodiment of the present invention discloses a double split gate power MOSFET device, such as figure 1 As shown, its conduction region includes several primitive cells arranged periodically, and each of the primitive cells includes a trench, a shielding electrode 103, a floating electrode 104, a trench gate electrode 106, and a source; wherein, the trench It is arranged in the epitaxial layer of the first conductivity type on the semiconductor substrate; the shielding electrode, the floating electrode and the trench gate electrode are arranged in parallel in the trench from bottom to top, and are separated from each other by a dielectric layer; the shielding electrode, the floating Both the empty electrode and the trench gate electrode are made of the second conductivity type material; the shielding electrode is connected to the source potential.
[0044] Compared with the prior art, in the double-split-gate power MOSFET device provided by this embodiment, t...
Embodiment 2
[0053] Another specific embodiment of the present invention discloses a method for preparing the double split gate power MOSFET device described in Embodiment 1, the flow chart is as follows image 3 As shown, the steps are as follows:
[0054] Step S1: Deposit an epitaxial layer of the first conductivity type on the semiconductor substrate, and form a trench on the epitaxial layer; considering the requirements of chip miniaturization, the expected effect is achieved with a smaller chip area, and the first conductivity type The thickness of the epitaxial layer is preferably 16-18 μm; the width of the groove is preferably 2.6-2.8 μm, and the depth is 7-9 μm.
[0055] Step S2: Prepare a shielding electrode and a floating electrode in parallel in sequence in the groove, the shielding electrode is located in the lower part of the groove, and the floating electrode is located in the middle and upper part of the groove; specifically:
[0056] Step S21: Deposit a dielectric layer 1 ...
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Abstract
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