Error extraction method for foreground digital calibration of assembly line analog-to-digital converter

Abstract

The invention provides an error extraction method for foreground digital calibration of an assembly line analog-to-digital converter, which comprises the following steps: acquiring a transmission curve of an assembly line analog-to-digital converter, and controlling an input signal to be within a subsection 0 of the transmission curve; when the error information of the i-th assembly line stage isextracted, setting the magnitude of the input signal to lock the output of all pre-stage comparators of the i-th assembly line stage in the assembly line analog-to-digital converter; according to theoriginal output code of the pipeline analog-to-digital converter, completing error extraction step by step in sequence from the rear stage to the front stage of the assembly line through self-adaptiveiteration. According to the method, when the error value is quantified, the capacitance mismatch error, the gain bandwidth error and the kickback error of each stage of the assembly line are extracted in the foreground through the fitting-based adaptive algorithm, an additional circuit is not needed, resources are saved, accurate quantification of the error value is realized, and digital calibration of the analog-to-digital converter of the assembly line can be conveniently realized.

Description

technical field [0001] The invention relates to the field of electronics, in particular to an error extraction method for front-end digital calibration of a pipeline analog-to-digital converter. Background technique [0002] The architecture of a pipelined analog-to-digital converter (ADC) is usually formed by cascading N low-resolution stage circuits. After the input signal is quantized by the first stage, n 1 Bit low-resolution quantization results, while outputting an enlarged margin to the second stage, and so on, each stage generates n i (i=1-N) bit low-resolution quantization results, and output the remainder as the input of the next stage. N low-resolution quantization results are synthesized into a final digital output by dislocation superposition. The stage circuit is composed of subADC and MDAC. The subADC is composed of multiple comparators to complete the low-resolution quantization function of the stage circuit. The MDAC includes two functional modules, subDAC...

AI Technical Summary

Problems solved by technology

Pipeline ADC background calibration can extract post-stage capacitor mismatch error, gain bandwidth error and kickback error, but it needs to increase analog auxiliary circuits and a large number of digital algorithm processing circuits

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