An Error Extraction Method for Front-end Digital Calibration of Pipeline Analog-to-Digital Converter

Abstract

The present invention provides an error extraction method for front digital calibration of a pipeline analog-to-digital converter, comprising: obtaining the transmission curve of the pipeline analog-to-digital converter, and controlling the input signal to be within subsection 0 of the transmission curve; when extracting the i-th When the error information of the pipeline stage is used, the size of the input signal is set to: lock the outputs of all previous comparators of the i-th pipeline stage in the pipeline analog-to-digital converter; according to the pipeline analog-to-digital converter The original output code of the original output code, from the back stage to the front stage of the pipeline, completes the error extraction step by step through adaptive iteration; in the present invention, when quantifying the error value, the capacitive loss at each stage of the pipeline is extracted by an adaptive algorithm based on fitting in the foreground. Matching error, gain bandwidth error and kickback error do not require additional circuits, save resources, realize accurate quantification of error values, and facilitate digital calibration of pipeline analog-to-digital converters.

Description

technical field [0001] The invention relates to the field of electronics, in particular to an error extraction method for front-end digital calibration of a pipeline analog-to-digital converter. Background technique [0002] The architecture of a pipelined analog-to-digital converter (ADC) is usually formed by cascading N low-resolution stage circuits. After the input signal is quantized by the first stage, n 1 Bit low-resolution quantization results, while outputting an enlarged margin to the second stage, and so on, each stage generates n i (i=1-N) bit low-resolution quantization results, and output the remainder as the input of the next stage. N low-resolution quantization results are synthesized into a final digital output by dislocation superposition. The stage circuit is composed of subADC and MDAC. The subADC is composed of multiple comparators to complete the low-resolution quantization function of the stage circuit. The MDAC includes two functional modules, subDAC...

AI Technical Summary

Problems solved by technology

Pipeline ADC background calibration can extract post-stage capacitor mismatch error, gain bandwidth error and kickback error, but it needs to increase analog auxiliary circuits and a large number of digital algorithm processing circuits

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