Digital timer topological structure and control method thereof

Abstract

The invention discloses a digital timer topological structure and a control method thereof. The topological structure comprises a plurality of D triggers, a NAND gate G1, a NAND gate G2 and a NAND gate G3. The output end of the NAND gate G2 is connected with the reset end of the first D trigger U1; the control end of the first D trigger U1 is connected with the output end of the NOT gate G1, the first input end of the NOT gate G1 is connected with the anti-phase output end of the last D trigger, and the second input end of the NOT gate G1 is connected with the in-phase output end of the secondD trigger U2; the control ends of the second D trigger U2 to the last D trigger are connected with the VDD end; the first input end of the NAND gate G3 is connected with the anti-phase output end ofthe first D trigger U1, and the second input end of the NAND gate G3 is connected with the anti-phase output end of the second D trigger U2. When the timer is applied to an I / F conversion circuit, thelinearity of an I / F conversion circuit is obviously improved, the power consumption of the circuit is reduced, and the conversion range of the circuit is increased.

Description

technical field [0001] The invention relates to the technical field of digital conversion circuits, in particular to a digital timer topology and a control method thereof. Background technique [0002] The current / frequency conversion (I / F) circuit is a conversion circuit that digitizes the current signal. It is often used in navigation control systems to convert the output current of the accelerometer into pulse output or other occasions that require high-precision analog / digital conversion. Since the output of the accelerometer head is a current analog signal, it must be converted into a digital signal through the I / F circuit before it can be processed by the computer in the inertial navigation system. Therefore, the actual measurement accuracy of the accelerometer is the combination of the accelerometer head and the I / F circuit. Accuracy, only by providing the accuracy of the I / F circuit can the accuracy of the output information of the accelerometer be maintained. The d...

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Problems solved by technology

Therefore, the timing time is fixed at one clock cycle CP, which cannot be adjusted according to the needs of I / F circuit design.

[0006]2. The conversion range is too small to meet the large range requirements of the accelerometer

[0008]3. The power consumption of the circuit is large, and the use environment is limited

[0009]Because the working range of the traditional I / F conversion circuit can only be half of the constant current source, in order to increase the conversion range, the output current of the constant current source must be increased, so This leads to a substantial increase in power consumption of the I / F conversion circuit, which in turn affects the application field of the I / F conversion circuit

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