Wafer-level packaging chip through-hole interconnection method and chip testing method
A technology of wafer-level packaging and testing methods, which is applied in the manufacture of electrical components, circuits, semiconductors/solid-state devices, etc., and can solve the problems of forming open circuits, poor electrical connection effects, and failure to form electrical connections, etc.
Active Publication Date: 2022-02-08
NINGBO SEMICON INT CORP
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Problems solved by technology
[0004] In the wafer-level packaging process, when the electrical connection is formed between the wafers, there may be problems such as air bubbles in the device, and the air bubbles will affect the effect of the electroplating, resulting in a poor electrical connection effect, or even an open circuit, which cannot be formed. effective electrical connection
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[0050] In order to thoroughly understand the present invention, detailed steps and structures will be provided in the following description, so as to explain the technical solution proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.
[0051] In the wafer-level packaging process, a chip can be attached to another wafer face-to-face through a die attach film (DAF), and then the metal pad of the chip can be bonded through silicon vias or other connection methods. (chip1) is connected to the metal pad (chip2) on the wafer. In this process, it is necessary to make through holes on the DAF film by dry etching. Then do PVD and electroplating in the through hole to complete the metal connection. Because the DAF film is attached to the front of the chip, the metal pad pits on the front of the chip will cause DAF to fail to fill th...
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Abstract
The present invention provides a method for through-hole interconnection of wafer-level packaged chips and a method for testing the chip. The method for through-hole interconnection of wafer-level packaged chips includes: providing a first chip; forming a passivation layer with a first opening to expose a first pad on the first chip; coating a polymer layer on the first chip and curing the polymer layer to fill the first pad An opening; providing a device wafer, bonding the first chip formed with a polymer layer on the device wafer; etching the device wafer and the polymer layer to form a first through hole, exposing The first pad; a plug is formed in the first through hole to be electrically connected to the first pad. The method can prevent undercuts due to air bubbles after etching, avoid the problems of conductive material deposition and metal connection failure, and further improve the performance and yield of packaging.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for through-hole interconnection of wafer-level packaging chips and a chip testing method. Background technique [0002] System in Package (SiP for short) combines multiple active components with different functions, as well as other components such as passive components, MEMS, and optical components, into one unit to form a single unit that can provide a variety of Functional systems or subsystems that allow integration of heterogeneous ICs are the best packaging integration techniques. Compared with System On Chip (SoC for short) packaging, SiP integration is relatively simple, the design cycle and market cycle are shorter, the cost is lower, and more complex systems can be realized. [0003] Compared with traditional SiP, wafer level package (wafer level package, referred to as WLP) is to complete the package integration process on the wafer, which has the adv...
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IPC IPC(8): H01L21/768
CPCH01L21/76877
Inventor 许嗣拓刘孟彬狄云翔
Owner NINGBO SEMICON INT CORP