3D memory device and manufacturing method thereof

Abstract

A method for manufacturing a 3D memory device is disclosed, comprising: forming a first stacked structure on a substrate, wherein the first stacked structure includes a plurality of interlayer insulating layers and a plurality of sacrificial layers stacked alternately; forming A plurality of channel pillars running through the first stacked structure; using a plurality of gate conductor layers to replace the plurality of sacrificial layers to form a stacked structure; wherein, the plurality of channel pillars and the plurality of gates A plurality of first gate conductor layers in the pole conductor layers form a plurality of storage transistors, and form a first selection transistor and a third gate conductor layer with the second gate conductor layer and the third gate conductor layer in the plurality of gate conductor layers respectively. The second selection transistor; the thickness of the plurality of first gate conductor layers is varied along the direction vertical to the substrate surface. The embodiment of the present invention can balance the difference in erasing speed caused by the different hole sizes of the channel pillars of the memory cells of different layers, thereby improving the reliability of the 3D memory.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a 3D memory device and a manufacturing method thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. In a three-dimensional memory device such as a 3D NAND flash memory, the memory array may include a core region having channel pillars. The channel pillar is formed in the channel hole vertic...

AI Technical Summary

Problems solved by technology

[0003] Then the existing channel hole etching process has the following problems: 1) the apertures of the channel holes are inconsistent, and the aperture of the upper part is generally larger than the aperture of the lower part

This results in the erase speed of memory cells in different layers

Because the aperture of the lower part of the channel hole is small, the electric field is more concentrated, and the erasing speed of the lower storage unit is faster, which not only increases the work difficulty for the circuit design, but also is not conducive to the reliability of the 3D storage device; 2) the overall process of the lower storage unit It is poorer than the process of the upper storage unit, resulting in the lower storage unit tending to have a lower read window

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