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Semiconductor integrated circuit, storage device, and error correction method

An error correction and integrated circuit technology, which is applied in the direction of error detection/correction, information storage, static memory, etc., can solve the problems of error correction circuit correction capability circuit scale limitation, low load correction capability error correction circuit, etc.

Pending Publication Date: 2019-11-01
LAPIS SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The correction capability of the error correction circuit (i.e., the ability to correct a bit disorder of several bits) is limited by the circuit size that can be loaded in the device
Therefore, there is a problem that an error correction circuit with a low correction capability can only be mounted in a device with a small circuit size that can be mounted.
In addition, there is a problem that even if an error correction circuit with a large circuit scale can be mounted, it is necessary to redesign the error correction circuit from scratch in order to improve the correction capability

Method used

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  • Semiconductor integrated circuit, storage device, and error correction method
  • Semiconductor integrated circuit, storage device, and error correction method
  • Semiconductor integrated circuit, storage device, and error correction method

Examples

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Embodiment 1

[0039] figure 1 is a block diagram showing the configuration of the storage device 100 of this embodiment. The storage device 100 is composed of a memory controller 11 , an error correction controller 12 , and a memory 20 . The memory controller 11 and the error correction controller 12 constitute a semiconductor integrated circuit 10 of one chip.

[0040] The memory controller 11 executes writing of data to the memory 20 and reading of data from the memory 20 . The memory controller 11 supplies the data read from the memory 20 to the error correction controller 12 .

[0041] The error correction controller 12 is a circuit that performs error correction on data read from the memory 20 by the memory controller 11 . Specifically, the error correction controller 12 corrects a bit error (so-called bit disorder) generated during data writing and reading. The error correction controller 12 includes a correction control section 13 , an error correction circuit 14 and an internal ...

Embodiment 2

[0063] Next, the storage device of the second embodiment will be described. The storage device of this embodiment has the same figure 1 The memory device 100 of the first embodiment shown has the same structure, but differs from the first embodiment in the structure of data stored in the memory 20 and the processing operation of the error correction process executed by the error correction controller 12 .

[0064] Figure 5 It is a diagram showing a structural example of data stored in the memory 20 in this embodiment. The 16-byte data part and the corresponding 4-byte CRC (Cyclic Redundancy Check, Cyclic Redundancy Check) code are associated and stored in the memory 20 . Then, a 2-byte parity bit is added to each of the 16-byte data portion and the 4-byte CRC code. In the following description, data obtained by adding a 2-byte parity bit to a 4-byte CRC code is referred to as "CRC data".

[0065] Thus, in this embodiment, 2-byte parity bits are added to the 16-byte data p...

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Abstract

The invention relates to a semiconductor integrated circuit, a storage device, and an error correction method. A semiconductor integrated circuit that can correct errors the number of bits of which exceeds the correction ability of the error correction circuit is provided. A semiconductor integrated circuit reads data from a memory, which stores the data including a data portion and a parity bit,and makes an error correction to the data. The semiconductor integrated circuit includes a memory controller for reading the data from the memory; and an error correction controller having an error correction circuit having the ability to correct a predetermined number of bits of errors. The error correction controller applies an error correction to the read data by the error correction circuit, and determines whether all errors contained in the data are corrected, based on the data portion and the parity bit of the data after the error correction. When not all the errors contained in the dataare determined to be corrected, the error correction controller applies an error correction by the error correction circuit, while sequentially inverting the data value of each bit of the data.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit for error correction of data and an error correction method. Background technique [0002] Error correction circuits are widely used in various systems that process data. For example, when data stored in a device is transferred to another device via a communication channel, errors such as bit confusion may occur. Therefore, an error correction circuit is often mounted on the device in order to correct the bit disorder generated during transfer. In addition, bit disorder occurs not only when data is transferred but also when data is stored or read from a storage medium such as a memory. Therefore, error correction circuits for error correction of data stored in a memory such as a flash memory using encoding means such as BCH codes have been proposed (for example, Patent Document 1, Patent Document 2). [0003] prior art literature [0004] patent documents [0005] Patent Document ...

Claims

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Application Information

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IPC IPC(8): H03M13/29
CPCH03M13/29G06F11/1004G11C29/52G06F11/1048G11C2029/0411G11C7/1006G06F11/1068
Inventor 坂东和彦宫崎聪司
Owner LAPIS SEMICON CO LTD