Semiconductor integrated circuit, storage device, and error correction method
An error correction and integrated circuit technology, which is applied in the direction of error detection/correction, information storage, static memory, etc., can solve the problems of error correction circuit correction capability circuit scale limitation, low load correction capability error correction circuit, etc.
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Embodiment 1
[0039] figure 1 is a block diagram showing the configuration of the storage device 100 of this embodiment. The storage device 100 is composed of a memory controller 11 , an error correction controller 12 , and a memory 20 . The memory controller 11 and the error correction controller 12 constitute a semiconductor integrated circuit 10 of one chip.
[0040] The memory controller 11 executes writing of data to the memory 20 and reading of data from the memory 20 . The memory controller 11 supplies the data read from the memory 20 to the error correction controller 12 .
[0041] The error correction controller 12 is a circuit that performs error correction on data read from the memory 20 by the memory controller 11 . Specifically, the error correction controller 12 corrects a bit error (so-called bit disorder) generated during data writing and reading. The error correction controller 12 includes a correction control section 13 , an error correction circuit 14 and an internal ...
Embodiment 2
[0063] Next, the storage device of the second embodiment will be described. The storage device of this embodiment has the same figure 1 The memory device 100 of the first embodiment shown has the same structure, but differs from the first embodiment in the structure of data stored in the memory 20 and the processing operation of the error correction process executed by the error correction controller 12 .
[0064] Figure 5 It is a diagram showing a structural example of data stored in the memory 20 in this embodiment. The 16-byte data part and the corresponding 4-byte CRC (Cyclic Redundancy Check, Cyclic Redundancy Check) code are associated and stored in the memory 20 . Then, a 2-byte parity bit is added to each of the 16-byte data portion and the 4-byte CRC code. In the following description, data obtained by adding a 2-byte parity bit to a 4-byte CRC code is referred to as "CRC data".
[0065] Thus, in this embodiment, 2-byte parity bits are added to the 16-byte data p...
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