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Multilayer chip packaging structure and preparation method thereof

A technology of multi-layer chip and packaging structure, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as large size, and achieve the effect of small package size and short signal transmission distance

Pending Publication Date: 2019-11-12
SHANGHAI XIANFANG SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Therefore, the embodiment of the present invention provides a multi-layer chip packaging structure and preparation method, which overcomes the defect of large volume of multi-layer chip stack packaging in the prior art

Method used

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  • Multilayer chip packaging structure and preparation method thereof
  • Multilayer chip packaging structure and preparation method thereof
  • Multilayer chip packaging structure and preparation method thereof

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Embodiment 1

[0044] An embodiment of the present invention provides a multi-layer chip packaging structure, including: a plurality of chip interconnection units 1, the plurality of chip interconnection units are composed of two flip-bonded interconnected chips; a bonding layer, the plurality of chip interconnection units The interconnection units are bonded through the bonding layer to form a multi-layer chip assembly unit 2 .

[0045] In the embodiment of the present invention, as figure 1 Shown is a chip interconnection unit 1, which includes two flip-bonded interconnected chips, one of which is used as a substrate chip, and the other chip is electrically connected to the substrate chip by soldering through flip-bonding. In the chip interconnection unit The two flip-bonded interconnected chips can be chips with the same function or chips with different functions, which can be selected according to their actual needs.

[0046] In the embodiment of the present invention, as figure 2 Sho...

Embodiment 2

[0053] Embodiments of the present invention provide a method for preparing a multilayer chip packaging structure, such as Figure 8 shown, including the following steps:

[0054] Step S10: Perform rewiring and pad preparation on the chip, such as Figure 9 As shown, it can be interconnected with other chips through rewiring and pads.

[0055] Step S20 : ​​Flip-bond interconnection of chips that have completed rewiring and pad preparation in pairs to form a preset number of chip interconnection units. In the embodiment of the present invention, in the soldering and interconnection process, one of the chips is used as the substrate chip, and the other chip is electrically connected to the substrate chip by flip-bonding, forming a figure 1 Chip interconnection unit shown. The two chips interconnected by reverse soldering in the chip interconnection unit may be chips with the same function or chips with different functions.

[0056] Step S30: Bonding and assembling a preset nu...

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Abstract

The invention discloses a multilayer chip packaging structure and a preparation method. The multilayer chip packaging structure comprises a plurality of chip interconnecting structures and bonding layers, wherein each of the chip interconnecting structures consists of two chips which are interconnected in a face-down bonding mode; the chip interconnecting units are bonded through the bonding layers to form the multilayer chip packaging unit. According to the multilayer chip packaging structure and the preparation method provided by the embodiment of the invention, multilayer chip stacking canbe realized, the packaging volume is small, the signal transmission distance is shorter, the multilayer chip packaging structure can be applicable for chips with same function and also can be applicable for chips with different functions, function signals of chips can be led out on the front and back sides of the packaging structure, and SiP and 3D packaging can be realized.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a multilayer chip packaging structure and a preparation method. Background technique [0002] In recent years, integrated circuit chip manufacturing technology has entered the nanometer range, and is challenging the "limit" of physics. The integration level of integrated circuits is getting higher and higher. The function is getting stronger and stronger, and the number of lead pins required is increasing. The rapid development of integrated circuits makes integrated circuit chip packaging substrates face enormous challenges. [0003] In 3D chip packaging or wafer-level packaging, the process generally used is to stack and package multi-layer chips, and the chips are interconnected through silicon vias or side leads. The packaging process is complex and the structure of the package is large. , can not meet the needs of integrated circuit chips with higher integ...

Claims

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Application Information

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IPC IPC(8): H01L25/065H01L21/98
CPCH01L25/0657H01L25/50H01L2225/06555
Inventor 任玉龙曹立强
Owner SHANGHAI XIANFANG SEMICON CO LTD