Multi-memory built-in self-test method based on multi-objective clustering genetic algorithm

Abstract

The invention relates to a multi-memory built-in self-test method based on a multi-objective clustering genetic algorithm, which comprises the following steps of: clustering memories to obtain a groupof compatible memory banks; wherein an integer vector encoding scheme is adopted by a standard circuit crapper for memory quantity and memory sharing test; generating an initial population; calculating target function value; crossover and variation; output decoding scheme; and testing memories.

Description

technical field [0001] The invention belongs to the field of integrated circuit testing, and relates to the optimized testing of multiple embedded memories in SOC by built-in self-test (Built in Self-Test, BIST) technology. Background technique [0002] In a system on chip (System on Chip, SOC), an embedded memory (usually an SRAM memory) occupies more than 95% of the chip area. Since the defect in the embedded memory will invalidate the whole chip, the Design for Test (DFT) of the embedded memory is very important. Built-in Self-Test (Built in Self-Test, BIST) is an increasingly effective and necessary DFT technique. BIST is a simple and low-cost method without affecting memory performance. But the BIST circuitry is implemented as additional logic on the chip, so the area cost becomes prohibitive for an SOC containing hundreds of memories. Furthermore, due to the power consumption limitation of the SOC, it is impossible to test all the memories at the same time. To test ...

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Problems solved by technology

In addition, in the genetic algorithm, the effect of the algorithm is highly dependent on the generation of the initial population, and the randomly generated initial population has the disadvantages of slow convergence speed and long running time.

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