Method of manufacturing capacitor assembly and semiconductor stacked packaging method
A technology for capacitor components and manufacturing methods, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components and other directions, can solve problems such as size reduction and package warpage, and achieve size reduction and flexibility. The effect of performance and simple preparation process
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[0026] see figure 1 , the present invention provides a capacitor assembly 100, the capacitor assembly 100 includes a substrate 10 and a capacitor structure and a via structure on the substrate 10. The capacitor structure includes a first upper via hole 17, a dielectric layer 12, a conductive layer 11, and a first lower via hole 19, and the via structure includes a second upper via hole 18, a conductive layer 11, and a second lower via hole 20, Wherein, the first and second lower via holes 19 and 20 are disposed in the substrate 10 and formed in the same step through the same process. The conductive layer 11 is deposited on the substrate 10 and has a plurality of discrete conductive patterns, and the plurality of discrete conductive patterns respectively correspond to and are physically connected to the first and second lower via holes 19 and 20 . The dielectric layer 12 covers the substrate 10 and the conductive layer 11 , and only has an opening at the bottom of the second u...
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