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Method of manufacturing capacitor assembly and semiconductor stacked packaging method

A technology for capacitor components and manufacturing methods, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components and other directions, can solve problems such as size reduction and package warpage, and achieve size reduction and flexibility. The effect of performance and simple preparation process

Inactive Publication Date: 2019-11-15
南通沃特光电科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For some integrated circuit packages with specific functions, it is often necessary to integrate capacitor devices. In the prior art, capacitors are often combined and packaged as an independent chip, or an embedded capacitor structure is formed in the wiring layer. The two packages Although it solves the specific function of the integrated circuit, it is not good for its size reduction, and it will also cause the package body to be warped due to stress

Method used

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  • Method of manufacturing capacitor assembly and semiconductor stacked packaging method
  • Method of manufacturing capacitor assembly and semiconductor stacked packaging method
  • Method of manufacturing capacitor assembly and semiconductor stacked packaging method

Examples

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Embodiment Construction

[0026] see figure 1 , the present invention provides a capacitor assembly 100, the capacitor assembly 100 includes a substrate 10 and a capacitor structure and a via structure on the substrate 10. The capacitor structure includes a first upper via hole 17, a dielectric layer 12, a conductive layer 11, and a first lower via hole 19, and the via structure includes a second upper via hole 18, a conductive layer 11, and a second lower via hole 20, Wherein, the first and second lower via holes 19 and 20 are disposed in the substrate 10 and formed in the same step through the same process. The conductive layer 11 is deposited on the substrate 10 and has a plurality of discrete conductive patterns, and the plurality of discrete conductive patterns respectively correspond to and are physically connected to the first and second lower via holes 19 and 20 . The dielectric layer 12 covers the substrate 10 and the conductive layer 11 , and only has an opening at the bottom of the second u...

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Abstract

The invention provides a method of manufacturing a capacitor assembly and a semiconductor stacked packaging method. A separate capacitor assembly module is used for integrated packaging, the packagingsize can be reduced, the packaging flexibility is improved at the same time, and the cost is reduced. The capacitor assembly comprises a capacitor structure and a through-hole structure. The manufacturing process is simple, two structures can be formed by using a conductive layer, etching depths are different, and electrical connection positions of upper through-holes are caused to be different.

Description

technical field [0001] The invention relates to the field of packaging of semiconductor devices, in particular to a method for manufacturing a capacitor component and a semiconductor stack packaging method. Background technique [0002] With the continuous improvement of integration, integrated circuit packaging adopts the package-on-package mode, that is, the POP structure. This kind of package is a three-dimensional package, which can flexibly control the stacking or lateral arrangement of chips to meet the requirements of small size. For some integrated circuit packages with specific functions, it is often necessary to integrate capacitor devices. In the prior art, capacitors are often combined and packaged as an independent chip, or an embedded capacitor structure is formed in the wiring layer. The two packages Although the specific function of the integrated circuit is solved, it is disadvantageous for the reduction of its size, and also causes the package body to be w...

Claims

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Application Information

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IPC IPC(8): H01L21/56H01L23/498H01L23/522H01L23/64H01L25/16
CPCH01L21/561H01L23/49816H01L23/5222H01L23/642H01L25/16H01L2224/16225H01L2924/181H01L2924/00012
Inventor 戴世元
Owner 南通沃特光电科技有限公司
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