[0026] see figure 1 , the present invention provides a capacitor assembly 100 , the capacitor assembly 100 includes a substrate 10 and a capacitor structure and a through hole structure on the substrate 10 . The capacitor structure includes a first upper through hole 17 , a dielectric layer 12 , a conductive layer 11 and a first lower through hole 19 , the through hole structure includes a second upper through hole 18 , a conductive layer 11 and a second lower through hole 20 , Wherein, the first and second lower through holes 19 and 20 are disposed in the substrate 10 and formed in the same steps by the same process. The conductive layer 11 is deposited on the substrate 10 and has a plurality of discrete conductive patterns corresponding to and physically connected to the first and second lower vias 19 and 20, respectively. The dielectric layer 12 covers the substrate 10 and the conductive layer 11 , and only has an opening at the bottom of the second upper via 18 , which exposes the conductive layer 11 . A low-K material layer 13 is formed on the dielectric layer 12 , and the first and second upper vias 17 and 18 are formed on the low-K material layer 13 . The bottom of the first upper via 17 is physically In contact with the dielectric layer 12 , the bottom of the second upper through hole 18 is in physical contact with the conductive layer 11 . The first upper through hole 17 serves as the upper plate of the capacitor structure, and the first lower through hole 19 and the conductive layer 12 serve as the lower plate of the capacitor structure.
[0027] For the manufacturing method of the above capacitor structure, see Figure 3-8 , see first image 3 , depositing a patterned conductive layer 11 on the substrate 10, wherein the substrate 10 is a silicon substrate, and the conductive layer 11 is any one of aluminum, copper, titanium, titanium nitride, tantalum, and tantalum nitride one or more combinations.
[0028] see Figure 4 , covering the substrate 10 and the conductive layer 11 with a dielectric layer 12, the dielectric layer 12 is a high-K material, such as ZrO 2 , Al 2 O 3 , Si 3 N 4 , HfO 2 , Y 2 O 3 , SiO 2 , Ta 2 O 5 , La 2 O 3 , TiO 2.
[0029] see Figure 5 , forming a low-K material layer 13 on the dielectric layer 12, and forming a first opening 14 and a second opening 15 in the low-K material layer 13 through the first etching, wherein the first opening 14 and the second openings 15 correspond to the patterned conductive layer 11 , and the bottoms of the first openings 14 and the second openings 15 expose the dielectric layer 12 . Wherein, the low-K material layer 13 is silicon oxide or silicon nitride.
[0030] see Image 6 and performing a second etching on the second opening 15 therein to etch away the dielectric layer at the bottom of the second opening 15 to form a third opening 16 , wherein the third opening 16 exposes the conductive layer 11 .
[0031] see Figure 7 , filling the first opening 14 and the third opening 16 with a conductive substance to form a first upper through hole 17 and a second upper through hole 18 , wherein the first upper through hole 17 and the conductive layer 11 pass through The dielectric layers 11 are separated, and the second upper through holes 18 are electrically connected to the conductive layers 11 .
[0032] see Figure 8 , opening from the back of the substrate 10 to form a fourth opening and a fifth opening, and filling the fourth opening and the fifth opening with a conductive substance to form a first lower through hole 19 and a second lower through hole 20 , wherein the first lower through-hole 19 corresponds to the first upper through-hole 17 one-to-one, the second lower through-hole 20 corresponds to the second upper through-hole 18 one-to-one, and the first and the second lower through holes are electrically connected to the conductive layer 11 .
[0033] In integrated circuit packaging, the capacitor assembly is package-friendly. For details, see figure 2 , the package body includes a first redistribution layer 28 having a first surface and a second surface, a first chip 22 and at least one of the above-mentioned capacitor components 100 are arranged on the first redistribution layer 28, the first redistribution layer 28 The chip 22 and the first and second lower vias 19 , 20 of the capacitor assembly 100 are electrically connected to the first redistribution layer 28 . The first plastic encapsulation layer 23 seals the first chip 22 and the capacitor element 100 , the top surface of the capacitor element 100 is flush with the top surface of the first plastic encapsulation layer 23 , and the first and second tops are connected to each other. The holes 17 and 18 are exposed from the top of the first plastic sealing layer 23 . The second redistribution layer 24 is formed on the first plastic sealing layer 23 , and the first and second upper through holes 17 and 18 are electrically connected to the second redistribution layer 24 . The second chip 25 is electrically connected on the second redistribution layer 24 through solder balls 26 , and the second chip 25 is sealed by a second plastic sealing layer 27 . In addition, the second surface also has external connection terminals 29 , such as solder balls, etc., which are electrically connected to the first redistribution layer 28 .
[0034] For the manufacturing method of the above-mentioned package structure, see Figure 9-13 , see first Figure 9 , the first chip 22 and a plurality of capacitor components 100 are fixedly placed on the temporary carrier 21 , wherein the capacitor components 100 are arranged around the first chip 22 .
[0035] see Figure 10 , the first chip 22 and the plurality of capacitor components 100 are sealed by the first plastic sealing layer 23 , wherein the top surface of the capacitor components 100 is flush with the top surface of the first plastic sealing layer 23 , and the first The first and second upper through holes 17 and 18 are exposed from the top of the first plastic sealing layer 23 .
[0036] see Figure 11 , a second redistribution layer 24 is formed on the first plastic sealing layer 23 , and the first and second upper through holes 17 and 18 are electrically connected to the second redistribution layer 24 . The second chip 25 is electrically connected on the second redistribution layer 24 through solder balls 26 , and the second chip 25 is sealed by a second plastic sealing layer 27 .
[0037] see Figure 12 , and peel off the temporary carrier 21 .
[0038] see Figure 13 , a first redistribution layer 28 is formed under the first plastic packaging layer 23, and the first chip 22 and the first and second lower through holes 19, 20 of the capacitor assembly 100 are electrically connected to the first Redistribution layer 28 . Finally, external connection terminals 29 are formed under the first redistribution layer 28 .
[0039] Finally, it should be noted that: obviously, the above-mentioned embodiments are only examples for clearly illustrating the present invention, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. However, the obvious changes or changes derived from this are still within the protection scope of the present invention.
