Supercharge Your Innovation With Domain-Expert AI Agents!

Background correction circuit and method for offset errors of latch type comparator

A technology for correcting circuits and comparators, applied in electrical components, analog/digital conversion calibration/testing, code conversion, etc., can solve problems such as increasing circuit complexity, and achieve circuit complexity reduction, wide correction range, and large correction range Effect

Active Publication Date: 2019-11-19
成都铭科思微电子技术有限责任公司
View PDF10 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Another defect of the two correction methods is that the correction needs to be controlled by a digital codeword. If the correction range is constant, the smaller the correction step size is to improve the correction accuracy, the greater the required codeword length, which increases the circuit. the complexity

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Background correction circuit and method for offset errors of latch type comparator
  • Background correction circuit and method for offset errors of latch type comparator
  • Background correction circuit and method for offset errors of latch type comparator

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] The present invention designs a background correction circuit for the offset error of the latch type comparator, without increasing the load on the output end of the latch type comparator, and only adding a pair of auxiliary input pair tubes at the drain end of the main input pair tube, such as figure 1 , figure 2 As shown, the following arrangement structure is adopted in particular: it includes a latch comparator 1 and a correction circuit 2 connected to each other, and the latch comparator 1 includes a main input pair tube, a tail current switch Q103, a load circuit, a reset circuit, In the AND gate and selector, an auxiliary input pair composed of MOS transistor Q104 and MOS transistor Q105 is provided at the drain end of the main input pair, and a tail current switch Q106 is connected to the source end of the auxiliary input pair, and the tail The current switch Q106 is commonly connected with the tail current switch Q103.

[0039] As a preferred setting scheme, ...

Embodiment 2

[0041] This embodiment is further optimized on the basis of the foregoing embodiments, and the same parts as the technical solutions of the preceding embodiments will not be repeated here, such as figure 1 , figure 2 As shown, further in order to better realize the background correction circuit of the offset error of the latch comparator described in the present invention, the following setting method is adopted in particular: the main input pair includes MOS transistors Q101 and MOS transistors Q102. The gate terminals of the MOS transistor 101 and the MOS transistor 102 are connected to a selector, the tail current switch Q103 is connected to the source terminal of the main input pair transistor, the gate terminals of the tail current switch Q103 and the tail current switch Q106 are both connected to the output terminal of the AND gate The drain end of the main input pair tube is also connected to the load circuit, the reset circuit is connected to the load circuit, and the...

Embodiment 3

[0045] This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same parts as the technical solutions of the foregoing embodiments will not be repeated here, such as figure 1 , figure 2 As shown, further in order to better realize the background correction circuit of the offset error of the latch comparator described in the present invention, the following setting method is adopted in particular: the selector adopts a two-to-one multiplexer, and the AND The gate uses a two-input AND gate.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a background correction circuit and a method for offset errors of a latch type compensator. The circuit comprises a latch type comparator (1) and a correction circuit (2) whichare connected with each other, the latch type comparator (1) comprises a main input geminate transistor, a tail current switch Q103, a load circuit, a reset circuit, an AND gate and a selector. An auxiliary input geminate transistor composed of an MOS transistor Q104 and an MOS transistor Q105 is arranged at the drain end of the main input geminate transistor, a tail current switch Q106 is connected to the source end of the auxiliary input geminate transistor, and the tail current switch Q106 and the tail current switch Q103 are connected together; the load of the output end of the latch typecomparator is not increased, and only one pair of auxiliary input geminate transistors is additionally arranged at the drain end of the main input geminate transistor.

Description

technical field [0001] The invention relates to the technical field of latch comparators, in particular to a background correction circuit and method for offset errors of latch comparators. Background technique [0002] As a quantization unit, a latch comparator is widely used in analog-to-digital converters. Due to the mismatch of device process parameters or layout parasitic parameters, the offset error of the comparator will be caused. In order to improve the accuracy of the comparator, it is necessary to correct the offset error of the comparator. [0003] There are mainly two kinds of offset correction methods for the existing latch comparator. One is to short-circuit the differential input of the comparator to the common-mode voltage during calibration, and then perform a latch operation on the comparator. According to the output result, adjust the load capacitance of one of the two differential outputs until the latch result up to inversion. The other is to short-...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
CPCH03M1/1014Y02B70/10
Inventor 杜翎刘学徐振涛杨荣彬胡国林
Owner 成都铭科思微电子技术有限责任公司
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com