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Semiconductor chip and processing method thereof

A processing method and semiconductor technology, applied in semiconductor devices, electrical solid devices, fluid velocity measurement, etc., can solve the problems of difficulty in process implementation and high cost, long silicon etching process time, and larger chip packaging area, etc., to achieve processing time The effect of shortening, low difficulty and wide process window

Active Publication Date: 2019-11-26
SENODIA TECH (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In the MEMS inertial sensing module, the most common way is to make a PAD for wiring on the outside of the component as mentioned above, and then connect it through metal wiring. The disadvantage is that making the PAD makes the area of ​​the chip package get bigger
[0005] Although the above method of guiding the PAD to the backside through TSV can effectively reduce the chip packaging area, the technical threshold of the TSV process is high, requiring multiple photomasks, and the process time of silicon etching is long, which makes the realization of the entire process difficult and expensive. higher

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  • Semiconductor chip and processing method thereof
  • Semiconductor chip and processing method thereof
  • Semiconductor chip and processing method thereof

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Embodiment 1

[0037] Such as image 3 As shown, the chip structure of this embodiment includes a first wafer 10, a second wafer 20, a third wafer 30, and a sensitive element 40, wherein the first wafer 10 and the third wafer 30 are stacked, and the two cooperate to define a cavity The body 60 , the sensitive element 40 is disposed in the cavity 60 . In some embodiments, the wafer where the sensitive element 40 is located is respectively bonded to the first wafer 10 and the third wafer 30 located on both sides thereof, so that the sensitive element 40 is arranged on the first wafer 10 and the third wafer 30. In the defined cavity 60; in some embodiments, the wafer where the sensitive element 40 is located is only bonded with the first wafer 10, and the first wafer 10 is bonded with the third wafer 30, so that the sensitive element 40 is arranged in the In the cavity 60 defined by the first wafer 10 and the third wafer 30 .

[0038] The first wafer 10 is provided with a first conductive lay...

Embodiment 2

[0083] Such as Figure 18 As shown, the chip structure of this embodiment includes a first wafer 10, a second wafer 20, a third wafer 30, and a sensitive element 40, wherein the first wafer 10 and the third wafer 30 are stacked, and the two cooperate to define a cavity The body 60 , the sensitive element 40 is disposed in the cavity 60 . In some embodiments, the wafer where the sensitive element 40 is located is respectively bonded to the first wafer 10 and the third wafer 30 located on both sides thereof, so that the sensitive element 40 is arranged on the first wafer 10 and the third wafer 30. In the defined cavity 60; in some embodiments, the wafer where the sensitive element 40 is located is only bonded with the first wafer 10, and the first wafer 10 is bonded with the third wafer 30, so that the sensitive element 40 is arranged in the In the cavity 60 defined by the first wafer 10 and the third wafer 30 .

[0084] The first wafer 10 is provided with a first conductive l...

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Abstract

The invention provides a semiconductor chip and a processing method thereof, the semiconductor chip comprises a first wafer, the first wafer is provided with a first conductive layer, and the first conductive layer extends to the edge of the first wafer; the semiconductor chip further comprises a second conducting layer, the second conducting layer is connected with the first conducting layer, andthe second conducting layer extends to the back face of the first wafer along the side wall of the first wafer.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor chip and a processing method thereof. Background technique [0002] MEMS (Micro Electro Mechanical System, Micro Electro Mechanical System) devices have been more and more widely used in products such as consumer electronics, medical treatment, and automobiles due to their small size, low cost, and good integration. Common MEMS devices include but are not limited to pressure sensors, magnetic sensors, microphones, accelerometers, gyroscopes, infrared sensors, etc. [0003] When the wafer is packaged and packaged, the bare chip needs to be bonded for electrical connection. In order to achieve this, if figure 1 As shown, an existing package structure includes die 1 (usually an ASIC) and die 2 (usually an inertial sensor, figure 1 Composed of multi-layer wafer bonding), both bare die 1 and die 2 need to reserve electrical connection contacts (PAD), and t...

Claims

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Application Information

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IPC IPC(8): B81B7/00B81C1/00
CPCB81B7/007B81C1/00301B81C1/00865
Inventor 邹波
Owner SENODIA TECH (SHANGHAI) CO LTD