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Nonvolatile memory processing method and device

A technology of non-volatile memory and processing method, applied in the field of non-volatile memory processing method and device, capable of solving problems such as unstable performance of non-volatile memory

Active Publication Date: 2019-12-31
GIGADEVICE SEMICON XIAN INC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the inventor found in the process of studying the above-mentioned technical solution that the above-mentioned technical solution has the following defects: the speed of establishing the WL (Word Line, word line) voltage when performing single-plane operation in the non-volatile memory of the dual-plane architecture, The speed at which the word line WL voltage is established is different from that of the dual plane operation, making the performance of the non-volatile memory of the dual plane architecture unstable

Method used

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  • Nonvolatile memory processing method and device

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Embodiment 1

[0034] refer to figure 1 , which shows a flow chart of a non-volatile memory processing method, which may specifically include the following steps:

[0035] In the embodiment of the present invention, taking the non-volatile memory NAND Flash as an example, the storage unit of the NAND Flash is as follows figure 2 As shown, the reference number 21 represents the control gate (Control gate, CG); the reference number 22 represents the floating gate (Floating gate, FG); the reference number 23 represents the drain (Drain); and the reference number 24 represents the source (Source).

[0036] When programming a non-volatile memory, by applying a high voltage to the control gate 21 and a low voltage to the drain 23, the electrons in the memory cell channel (Channel) can be written into the floating gate 22, completing programming operation.

[0037] exist image 3 In, a NAND Flash with a dual plane architecture is shown, image 3 The number 31 represents one of the planes, whic...

Embodiment 2

[0052] refer to Figure 5 , showing a block diagram of a non-volatile memory processing device, the device may specifically include:

[0053] a receiving module 510, configured to receive an operation instruction for the non-volatile memory;

[0054] The control module 520 is configured to simultaneously turn on the control switches corresponding to the plurality of storage boards according to the operation instruction.

[0055] Preferably, the word line WL of each of the planes is connected to the control switch corresponding to each of the planes; each of the control switches controls the start or stop of each of the planes through each of the WLs.

[0056] Preferably, each of the planes also corresponds to: a word line control area, a bit line control area;

[0057] The word line control area is used to control the word line WL voltage of the plane;

[0058] The bit line control area is used to control the voltage of the bit line BL of the plane.

[0059...

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Abstract

Embodiments of the invention provide a nonvolatile memory processing method and device. The method comprises the steps of receiving an operation instruction for a nonvolatile memory; and according tothe operation instruction, turning on the control switches corresponding to the plurality of memory boards simultaneously. According to the embodiment of the invention, when the multi-plane nonvolatile memory works, the control switches corresponding to all planes in the multi-plane nonvolatile memory are turned on at the same time; the load introduced by the word line WL during the single plane operation is the same as the load during the multi-plane operation; the speed of establishing the word line WL voltage during single-plane operation is the same as the speed of establishing the word line WL voltage during double-plane operation, so that the uniformity of the multi-plane nonvolatile memory during working is ensured.

Description

technical field [0001] The present invention relates to the technical field of memory processing, in particular to a nonvolatile memory processing method and device. Background technique [0002] With the continuous development of portable electronic products, there are higher requirements for the capacity and speed of non-volatile memory. In order to increase the capacity and speed of non-volatile memory, more chips use multiple plane architecture. The Plane architecture is an internal architecture of the non-volatile memory, and the plane is a unit managed by the control unit of the non-volatile memory. If the non-volatile memory has only 1 plane, it has only one control unit, so it can only do one thing at the same time. If the non-volatile memory has 2 or more planes, it has 2 or more control units. A unit that can do 2 or more things at the same time, such as reading, writing and erasing at the same time. [0003] In the prior art, taking the non-volatile memory NAND...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/08G11C16/24G11C16/04
CPCG11C16/0483G11C16/08G11C16/24
Inventor 马思博李杨舒清明
Owner GIGADEVICE SEMICON XIAN INC
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