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Die-Level Error Recovery Scheme

A die and memory technology, applied in the field of die-level error recovery solutions, which can solve problems such as constraining device operability

Active Publication Date: 2021-06-04
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Resources dedicated to storing such data may not be available for other uses, and thus may constrain device operability

Method used

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  • Die-Level Error Recovery Scheme
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Examples

Experimental program
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Embodiment Construction

[0015] A memory device may be designated to store parity data. Parity data can be stored or backed up in non-volatile memory, or in volatile memory powered by an additional power supply, for example, to prevent data loss due to power loss or component defect. In some cases, the memory device may store parity data for restoring the data of the additional memory device as a means of backing up the data of the additional memory device. However, in many cases, backing up an entire memory device may result in overprovisioning of memory and waste of resources. Thus, as described herein, a die-level redundancy scheme may be employed, wherein parity data associated with a particular die (rather than an entire memory device) may be stored.

[0016] In general, the hardware of a computing system includes processing circuitry and memory, implemented, for example, using one or more processors and / or one or more memory devices (eg, chips or integrated circuits). During operation of the c...

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Abstract

This application relates to a die-level error recovery scheme. Methods, apparatus, and systems for error recovery in memory devices are described. A die-level redundancy scheme may be employed where parity data associated with a particular die may be stored. An example apparatus may include a printed circuit board having memory devices each disposed on a planar surface of the printed circuit board. Each memory device may include two or more memory dies, channels communicatively coupled to the two or more memory dies, and a memory controller communicatively coupled to the plurality of channels. The memory controller can deterministically maintain a die-level redundancy scheme via data transfers through the plurality of channels. The memory controller can also generate parity data associated with the two or more memory dies in response to a data write event.

Description

technical field [0001] This application relates to a die-level error recovery scheme. Background technique [0002] This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the invention that are described and / or claimed below. It is believed that this discussion helps to provide the reader with background information to facilitate a better understanding of various aspects of the invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art. [0003] In general, computing systems include processing circuitry (eg, one or more processors or other suitable components) and memory devices (eg, chips or integrated circuits). One or more memory devices may be implemented on a memory module, such as a dual inline memory module (DIMM), to store data accessible to processing circuitry. For example, based on user input to the computing system, the pr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/07G06F11/10G06F3/06
CPCG06F3/0619G06F3/0658G06F3/0688G06F11/0727G06F11/0793G06F11/1032G06F11/1068G06F11/108G11C11/005G11C11/22G11C13/0004G11C16/0483G11C29/52G11C29/74G11C2029/0409G11C2029/0411G06F3/0659G06F3/0679G11C13/004G11C13/0069G11C29/42G11C29/78G11C2213/71H05K1/181H05K2201/10159H05K2201/10522
Inventor 里什米·巴苏
Owner MICRON TECH INC