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Analog circuit optimization algorithm based on multi-objective acquisition function integrated parallel Bayesian optimization

A multi-objective integration and multi-objective optimization technology, which is applied in the field of analog circuit optimization algorithms based on multi-objective acquisition function integration parallel Bayesian optimization, can solve the problems of small number of simulations and inability to make full use of parallel resources, and achieve good optimization results Effect

Pending Publication Date: 2020-02-04
FUDAN UNIV
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Problems solved by technology

[0006] Bayesian optimization methods require fewer simulations during optimization, however, Bayesian optimization is a serial optimization algorithm that, during each iteration, optimizes an acquisition function constructed from a Gaussian process model ( Acquisition function) to select points for circuit simulation, so parallel resources cannot be fully utilized

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  • Analog circuit optimization algorithm based on multi-objective acquisition function integrated parallel Bayesian optimization
  • Analog circuit optimization algorithm based on multi-objective acquisition function integrated parallel Bayesian optimization
  • Analog circuit optimization algorithm based on multi-objective acquisition function integrated parallel Bayesian optimization

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Embodiment Construction

[0067] Now, the method of the present invention is described through the implementation process of specific calculation examples.

[0068] The Multi-Objective ACquisition function Ensemble (MACE) method proposed in this application is compared with other parallel Bayesian optimization algorithms. The methods to be compared include the BLCB algorithm proposed in the prior art [8], the local penalty (LP) algorithm proposed in the prior art [9], the qKG method proposed in the prior art [10] and the prior art [ 11] proposed qEI method.

[0069] The present invention uses three calculation examples to test the MACE algorithm. The first calculation example is a general analytical test function, and the other two calculation examples are actual analog circuit netlists, including an operational amplifier and a power amplifier.

[0070] Implementation example 1

[0071] Eight general analytical test functions are used to test the MACE algorithm. The dimensions and computational searc...

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Abstract

The invention belongs to the field of automatic optimization of analog circuit design parameters in integrated circuit design, in particular to a Gaussian process model-based a circuit optimization method using a Batch Bayesian optimization algorithm. According to the method, in each iteration, a Gaussian process model is firstly constructed, then a plurality of acquisition functions are constructed by the Gaussian process model, multi-objective optimization is carried out on the acquisition functions to obtain Pareto front edges of the acquisition functions, and a plurality of points for circuit simulation are selected from the Pareto front edges. According to the method, the simulation frequency of the circuit in the optimization process can be greatly reduced, analog circuit design parameters meeting the performance requirements are obtained, and meanwhile circuit optimization can be accelerated through the parallel optimization technology.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and relates to an automatic optimization method for analog circuit design parameters in integrated circuit design, in particular to a circuit optimization method based on a Gaussian process model (Gaussian Process) and using a parallel Bayesian optimization (BatchBayesian Optimization) algorithm. The method can greatly reduce the number of circuit simulations in the optimization process, obtain analog circuit design parameters that meet performance requirements, and can accelerate circuit optimization by using parallel optimization technology. Background technique [0002] Digital integrated circuits have now entered the 10nm process node, and the feature size of analog circuits is also rapidly approaching the 10nm node to reduce power consumption, reduce area, improve performance and integration. With the adoption of new technology, the transistor model in analog circuit design is becomi...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/36G06F30/373G06F30/20
Inventor 曾璇周电杨帆严昌浩吕文龙
Owner FUDAN UNIV
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