Package substrate structure and its bonding method

Abstract

The invention provides a packaging substrate structure, which includes a first substrate, a second substrate, a plurality of conductive columns and an adhesive layer. The first substrate includes a plurality of blind holes and a plurality of pads. The blind holes and the pads are disposed on the first substrate and filled into the blind holes. The second substrate is arranged relative to the first substrate. Each conductive column is located between the first substrate and the second substrate, electrically connects each pad and the second substrate, and each conductive column fills each blind hole. The adhesive layer is disposed between the first substrate and the second substrate, and the adhesive layer fills the gaps between the conductive columns. A bonding method of the package substrate structure is also proposed.

Description

technical field [0001] The invention relates to a package technology, in particular to a package substrate structure and a bonding method thereof. Background technique [0002] With the evolution of semiconductor packaging technology, different packaging methods have been developed for semiconductor devices, such as wire bonding, flip chip or hybrid (flip chip matching) wired). In the process of pursuing high performance and shrinking package volume, the volume of thin lines is becoming more and more refined, and the resistance value will increase, thereby reducing performance. [0003] At present, there is a packaging technology that uses copper structures to make thin lines to reduce resistance and perform bonding. However, the implementation conditions that can be achieved by the current copper bonding are a temperature of 300° C. to 450° C. and a pressure of up to 300 MPa, and an annealing treatment is usually required after bonding. In addition, before bonding, the s...

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Problems solved by technology

In addition, before bonding, the surface of the copper structure needs to be well cleaned and must undergo a chemical-mechanical planarization (CMP) process to obtain a flat surface, so the process is complicated and the manufacturing cost cannot be reduced.

In addition, when fabricating thin lines on the substrate, the asymmetric structure may cause the substrate material to warp, resulting in poor manufacturing yield.

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