Energy-saving switch switching circuit suitable for low-voltage SAR ADC design and method of energy-saving switch switching circuit

Abstract

The invention discloses an energy-saving switch switching circuit suitable for low-voltage SAR ADC design and a method of the energy-saving switch switching circuit, and belongs to the technical fieldof integrated circuit design. The circuit comprises a P-end sampling switch (101), an N-end sampling switch (102), a DAC array, a P-end switch array (107), an N-end switch array (108), a comparator (109) and an SAR logic unit (110). The DAC array comprises a P-end MSB sub-array (103), a P-end LSB sub-array (104), an N-end MSB sub-array (105) and an N-end LSB sub-array (106). The MSB split structure and the combination and separation technology are combined so that the switching energy of the switch can be reduced by 99.76% in comparison with the traditional switching algorithm, the use of thethird reference level can be avoided, and the circuit has the advantages of energy and linearity and is especially suitable for the design of the low-voltage ADC.

Description

technical field [0001] The invention relates to an energy-saving switching circuit suitable for low-voltage SAR ADC design and a method thereof, belonging to the technical field of integrated circuit design. Background technique [0002] The reduction of process size and the reduction of power supply voltage make the highly digitized SAR ADC architecture the best choice for implementing low-power analog-to-digital converters, where the switching energy of the DAC array accounts for a large proportion of the power consumption in the entire SAR ADC design. bigger and bigger. Therefore, research on algorithms for reducing switching energy has become a hot topic. [0003] There are many deficiencies in the early switching algorithm, such as the monotonic algorithm causes excessive changes in the common-mode level, which causes the dynamic offset of the comparator, and the algorithm based on Vcm requires an additional third-level generation circuit and common-mode transmission s...

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Problems solved by technology

[0003] There are many deficiencies in the early switching algorithm, such as the monotonic algorithm causes excessive changes in the common-mode level, which causes the dynamic offset of the comparator, and the algorithm based on Vcm requires an additional third-level generation circuit and common-mode transmission switch, so it is not suitable for low-voltage switching. Voltage Design[C.Liou and C.Hsieh.A 2.4-to-5.2fJ / conversion-step 10b 0.5-to-4MS / s SAR ADC with charge-average switching DAC in 90nm CMOS.IEEEInternational Solid-State Circuits Conference Digest of Technical Papers, 2013]. Another class of switching algorithms focuses on reducing switching energy by skipping unnecessary intermediate switching processes [Z.Ding, X.Zhou and Q.Li.A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator. IEEE Journal of Solid-State Circuits, 2019], but the additional input voltage range detection circuit complicates the design

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