Manufacturing method of shield gate trench power device

Abstract

The invention provides a manufacturing method of a shield gate trench power device. The method comprises the following steps of: providing a substrate, forming at least one first trench in a device unit region of the substrate, forming at least one second trench in an electrode connection region of the substrate, and forming first dielectric layers on the side walls and the bottoms of the first trench and the second trench; forming a shielding gate in the first trench, partially filling the first trench with the shielding gate, and filling the second trench with a conductive material; forminga second dielectric layer which fills the first trench and covers the surface of the substrate and the conductive material; removing the second dielectric layer on the device unit region by adopting adry isotropic etching process, and exposing a part of the first trench; forming a gate in the first trench. According to the invention, before the gate is formed, the second dielectric layer on the device unit region is removed through dry isotropic etching, and part of the first trench is exposed, so that compared with the traditional wet etching removal, the process time is shortened, and the undercutting problem is effectively reduced and even avoided.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for manufacturing shielded gate trench power devices. Background technique [0002] Since the invention of power MOS technology, the technology has achieved many important developments and great progress. In recent years, new device structures and new manufacturing processes of power MOS technology have emerged continuously to achieve two basic goals: maximum power handling capability and minimum power loss. Trench MOSFET (Trench MOS) technology is one of the most important technological driving forces to achieve this goal. Initially, Trench MOS technology was invented to increase the channel density of planar devices to improve the current handling capability of the device, but its channel density and drift region resistance are not yet ideal. [0003] Therefore, the industry has further proposed a new Trench MOS structure. The new Trench MOS structure ...

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Problems solved by technology

[0007] However, wet etching is used to remove part of the second dielectric layer 123, and the etching takes a long time, which will cause the following problems: first, the photoresist is soaked in the wet etching solution for a long time, and the adhesion is reduced , so that undercutting occurs at the edge of the covered area, such as Figure 2A As shown, the position of this undercut will produce conductive material such as polysilicon residue during the formation process of the gate 112, causing the wrong connection between the gate 112 and the conductive material 121, such as Figure 2B As shown; second, long-term soaking of the photoresist will cause defects in the photoresist itself, which will bring hidden dangers to the subsequent process; third, when the photoresist is removed after wet etching, photoresist residues are prone to occur

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