Bonding pad structure, chip and method thereof
A pad and chip technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of large parasitic capacitance, limited IO working speed, and many metal layers, so as to reduce parasitic capacitance, improve IO working speed, discharge short path effect
Inactive Publication Date: 2020-04-28
伟芯科技(绍兴)有限公司
View PDF5 Cites 0 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
For high-speed IO design, due to its high signal working speed, the parasitic capacitance of IO pad is required to be very small to realize high-speed IO design. Therefore, the traditional IO pad structure has many metal layers and large parasitic capacitance, which limits the further improvement of IO working speed.
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0027] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.
[0028] An embodiment of the present invention provides a pad structure, such as figure 1 As shown, it includes a front metal layer 1, a back metal layer 2, and a pad 3. The front metal layer 1 and the back metal layer 2 are respectively located on the front and back sides of the chip silicon chip 4, and the front side of the back metal layer 2 forms a solder joint. Disc 3: The present invention uses few metal layers to realize the pad design, therefore, the parasitic capacitance of pad 3 is greatly reduced, which can be reduced by 80% at most, so that high-speed design of IO can be realized and the...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
| Property | Measurement | Unit |
|---|---|---|
| diameter | aaaaa | aaaaa |
| diameter | aaaaa | aaaaa |
| diameter | aaaaa | aaaaa |
Login to View More
Abstract
The invention discloses a bonding pad structure, a chip and a forming method thereof, and the bonding pad structure is characterized in that the bonding pad structure comprises a front metal layer, aback metal layer and a bonding pad, the front metal layer and the back metal layer are located on the front surface and the back surface of a chip silicon wafer respectively, and the bonding pad is formed in the front surface of the back metal layer. According to the invention, the design of the bonding pad is realized by using few metal layers, so that the parasitic capacitance of the bonding padis greatly reduced and can be reduced by 80% at most, the high-speed design of IO can be realized, and the IO working speed is improved; meanwhile, the design of the bonding pad is realized by usingfew metal layers, so that the path from the chip device to the bonding pad is remarkably shortened, the discharge path is shorter during electrostatic discharge (ESD), the resistance is lower, and theESD protection capability can be remarkably improved.
Description
technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a pad structure, a chip and a method thereof. Background technique [0002] When the integrated circuit (chip) is packaged, it is necessary to connect the bare die (chip) and the outer package shell through the bonding wire. The die is designed with a bonding pad, and there is an exposed metal layer on the pad, so it can be connected with the bonding wire. Metal contacts are formed between metal interconnections to conduct electrical signals, and the chip IO pad is connected to the pins of the package shell. The pad needs to be connected to the underlying device in the chip. Usually, the pad is designed with the highest layer of metal in the technology. [0003] In the traditional technology, an integrated circuit device is formed on a chip silicon wafer (wafer / die), and the device is connected to the first metal layer through a contact hole, and the first...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/488H01L23/498H01L21/48
CPCH01L21/4814H01L21/4853H01L21/486H01L23/488H01L23/49811H01L23/49827H01L23/49838
Inventor 马树永
Owner 伟芯科技(绍兴)有限公司