FPGA Frequency Doubling Method Based on Phase Superposition Method
A technology of phase superposition and frequency doubling, applied in power oscillators, electrical components, etc., can solve the problems of difficulty in speeding up, excessive resource occupation, etc., to achieve improved performance, low test cost, good universality and innovation. Effect
Active Publication Date: 2021-06-01
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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[0004] The present invention provides an FPGA frequency multiplication method based on a phase superposition method in order to solve the problem that it is difficult to increase the speed in the existing FPGA development, and it is easy to cause excessive resource occupation when doing pipeline processing
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Embodiment 1
[0041] Please refer to Figure 1 to Figure 4 , the present embodiment provides a kind of FPGA frequency doubling method based on phase superposition method, and this method comprises the following steps:
[0042] S1. Generate 8 original clock signals I with a phase difference of 22.5 degrees in the PLL clock module of the FPGA. The frequency of each original clock signal I is 1 / 8 of the expected frequency, and the eight original clock signals I are different Or processing, so that the PLL clock module of the FPGA can obtain a high-frequency clock signal that has been multiplied by 8,
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The invention discloses an FPGA frequency doubling method based on a phase superposition method, which relates to the technical field of digital signal processing. The method first performs an octave frequency multiplication operation of the FPGA, and if the stability of the obtained frequency doubling signal cannot meet the needs of users, the method is then performed. For quadruple frequency multiplication operation, if the stability of the obtained frequency multiplication signal still cannot meet the needs of users, the double frequency operation will be carried out. After each frequency multiplication signal is obtained, the signal stability test will be used to determine whether it is stable. The frequency operation process is to generate the original clock signal corresponding to the frequency multiplier K in the PLL clock module of the FPGA, and the phase difference is 180 / K degrees. The frequency of each original clock signal is 1 / K of the expected frequency, and the K Exclusive OR processing is performed on the original clock signal of one channel, so that the PLL clock module of the FPGA can obtain a high-frequency clock signal that has been multiplied by K. This method greatly reduces the occupancy of system logic units without losing speed, and can be used on small FPGAs with lower costs.
Description
technical field [0001] The invention relates to the technical field of digital signal processing, in particular to an FPGA frequency doubling method based on a phase superposition method. Background technique [0002] In recent years, FPGAs have been widely used in communication electronics, informatics, and computer science, such as high-speed FFT, parallel computing acceleration, and signal sampling. In some low-occupancy, high-speed development, it is often necessary to increase the operating frequency and high Frequency FPGAs are often expensive and have excess resources, which cause unnecessary waste in engineering. For example, in Xilinx's 7 series FPGAs, Spartan-7 is the most basic model, which has the advantages of small package and low price, but its overall work The frequency is not high, and although the high-performance Virtex-7 series has a higher speed, it is still limited by the frequency output of the PLL core, and it is expensive and has more resources, whic...
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IPC IPC(8): H03B19/00
CPCH03B19/00
Inventor 孙旭吴鹏黄广超于文卓
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA



