Transistor structure for electrostatic protection and manufacturing method thereof

Abstract

Disclosed is a transistor structure for electrostatic protection and a manufacturing method thereof. The transistor structure includes: a substrate and a first doped region formed on the upper part of the substrate; a plurality of field oxide layers formed on the surface of the substrate; The second doped region formed in the middle of the first doped region, the doping type of the first doped region is opposite to that of the second doped region; the second doped region formed in the upper part of the first doped region An N-type well region, a first P-type well region, a second P-type well region, and a second N-type well region; the first N-type well region and the second N-type well region are formed respectively An N+ region and a second N+ region; and a P+ region formed on the upper part of the first doped region and above the second doped region, wherein the second doped region is located in the first P-type between the well region and the second P-type well region, and are respectively connected to the first P-type well region and the second P-type well region. The device can maintain good electrostatic protection capability and high robustness.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a transistor structure for electrostatic protection and a manufacturing method thereof. Background technique [0002] ESD (Electro-Static discharge, electrostatic discharge) is an objective natural phenomenon that accompanies the entire cycle of the product. From the manufacturing, packaging, testing to the application stage of the chip, its external environment and internal structure will accumulate a certain amount of charge, and will be threatened by static electricity at any time. Therefore, in chip design, ESD protection devices need to be placed on each pin to protect the chip from power-off and power-on states. [0003] In actual design, each pin of the chip needs to be well protected against ESD. As the number of chip pins increases, the area occupied by the ESD device will also increase. Therefore, there is a need to continuously improve the robustness o...

AI Technical Summary

Problems solved by technology

However, its ability to discharge ESD current is average, so in a chip with many pins, it is necessary to waste a large area to design multiple protective devices

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