Interconnection method for semiconductor structure and semiconductor structure
A technology of semiconductor and stacked structure, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., and can solve the problems of complex manufacturing procedures and low yield of semiconductor structures
Pending Publication Date: 2020-06-09
CHANGXIN MEMORY TECH INC
View PDF0 Cites 0 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
[0006] The purpose of the present disclosure is to provide an interconnection method and semiconductor structure for semiconductor structures, which are used to overcome the problems of complex manufacturing procedures and low yields of semiconductor structures caused by limitations and defects of related technologies at least to a certain extent
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details being omitted, or other methods, components, devices, steps, etc. may be adopted. In other instances, well-known technical solution...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
The invention provides an interconnection method for a semiconductor structure and the semiconductor structure. The interconnection method comprises the steps: a stacking structure is provided, wherein the stacking structure comprises multiple layers of bonded wafers or chips, each wafer or chip comprises a substrate and a wiring layer, and each wiring layer comprises multiple metal wires; a silicon through hole is formed in the stacking structure, wherein the silicon through hole is connected with a first number of metal wires; insulation processing is carried out on a second number of metalwires connected with the silicon through hole, wherein the second number is smaller than the first number; and a conductive material is filled in the silicon through hole. According to the interconnection method disclosed by the invention, the semiconductor structure for electrically connecting each layer of wafer or chip in the stacking structure can be manufactured through one mask etching process.
Description
technical field [0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular, relates to an interconnection method of a semiconductor structure and a semiconductor structure. Background technique [0002] In the integrated circuit manufacturing process, stacking multiple chips and establishing mechanical and electrical connections is an important method to reduce the volume of the integrated circuit. The current practice is to first make TSV (ThroughSilicon Vias) for each chip that needs to be stacked, then form the bump (Micro-Bump) of each TSV, and finally use the chip-to-chip or chip-to-wafer method for positioning Bonding, using each bump and TSV to realize the electrical connection between the upper chip and the lower chip. [0003] First, in the wafer-to-wafer or wafer-to-wafer bonding process, low efficiency leads to high cost. In addition, it is necessary to make TSVs and bumps for each chip in advance. During ...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More IPC IPC(8): H01L23/48H01L21/768
CPCH01L21/76898H01L23/481H01L2224/11H01L2224/13025
Inventor 吴秉桓
Owner CHANGXIN MEMORY TECH INC