Circuit, device and method for testability design of many-core computing chip

Abstract

The invention discloses a circuit, device and method for the testability design of many-core computing chips. The many-core computing chips have preset classification marks and include a plurality of computing cores. Each computing core is assigned a different core ID; when testing, control the test process of each computing core, including the selection of test data and test process control; and send the test data to the computing core, test each computing core according to the test data, and according to the test results , record the number of failed computing cores and the corresponding core IDs; finally modify the classification marks of the many-core computing chips according to the test results and repair them; the effect is: by detecting the computing results of each computing core, it can be judged that the computing core is functioning correctly In addition, the test process is automatically completed by the hardware, which ensures the timeliness of the test.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to a circuit, device and method for testability design of many-core computing chips. Background technique [0002] With the rise of popular fields such as blockchain and AI, its huge computing demand has driven a wave of research on multi-core computing chips, such as GPUs, AI chips, digital cryptocurrency mining chips, and so on. These chips have a common feature, they all achieve the purpose of high computing power on a single chip by stacking many identical computing cores. [0003] The chip manufacturing process is usually not ideal. Due to various factors, some manufacturing defects or deviations will be introduced. In the chip design stage, it is necessary to provide certain testing methods, that is, testability design, so that testing and screening can be performed after the chip is produced. . With the evolution of integrated circuit technology, the number of computin...

AI Technical Summary

Problems solved by technology

[0004] At present, the commonly used testability design methods include scan chain (Scan Chain) test, software test, etc., but the advantage of scan chain (Scan Chain) technology is that the test speed is fast and the coverage is complete, but it needs to introduce additional circuit area and power consumption. At the same time, problems such as current limitation and heat generation are faced during testing, especially on high-performance many-core computing chips; software testing is a low-cost method, but its disadvantage is that the test speed is slow and the timeliness is poor

[0005] Although there is a built-in self-test (BIST, Build-In-Self-Test) circuit in the prior art, it still has no corresponding real-speed test and automatic classification of chip performance. Related patent works in this area

Images