Unlock instant, AI-driven research and patent intelligence for your innovation.

System and method for aligning semiconductor device reference images and test images

A technology of test images and reference images, which is applied in semiconductor/solid-state device testing/measurement, semiconductor/solid-state device manufacturing, image enhancement, etc., and can solve problems such as inability to flexibly handle large image offsets

Active Publication Date: 2020-06-19
KLA CORP
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Furthermore, the hardware RTA process can only align images with small initial offsets and cannot flexibly handle large image offsets (eg 20 pixels) due to hardware limitations

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • System and method for aligning semiconductor device reference images and test images
  • System and method for aligning semiconductor device reference images and test images
  • System and method for aligning semiconductor device reference images and test images

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] Reference will now be made in detail to the disclosed subject matter which is illustrated in the accompanying drawings.

[0034] generally refer to Figures 1A to 11 , describing a system and method for aligning a reference image and a test image of a semiconductor device according to one or more embodiments of the present invention.

[0035] Embodiments of the present invention relate to a system and method for aligning semiconductor device reference images and test images through coarse alignment steps and fine alignment steps. Embodiments of the invention also relate to a method for measuring data from selected optical scans and wafer arrangements (e.g., same optical scan, different optical scan, optical scan / design data, same die row, different die row, same wafer , different wafers, or the like) systems and methods for offsetting Run Time Alignment (RTA) blocks. Embodiments of the invention also relate to a system and method for measuring individual offsets using...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A method may include, but is not limited to, receiving a plurality of reference images of a wafer. The method may include, but is not limited to, receiving the plurality of test images of the wafer. The method may include, but is not limited to, aligning the plurality of reference images and the plurality of test images via a coarse alignment process. The method may include, but is not limited to,aligning the plurality of reference images and the plurality of test images via a fine alignment process after alignment via the coarse alignment process. The fine alignment process may include measuring individual offsets and correcting individual offset data between at least one of the plurality of reference images and the plurality of test images.

Description

[0001] Cross References to Related Applications [0002] This application claims under 35 U.S.C. §119(e) that Hong Chen, Michael Cook, Pavan Kumar and Wu Kennong filed on November 7, 2017 (Kenong Wu) is the inventor of a paper titled "Alignment of a Software ALGO-Based Algorithm for Aligning Test and Reference to 05 Pixel 3 Sigma Everywhere on a Wafer (SOFTWARE ALGO BASED ALIGNMENT TO ALIGN TEST ANDREFERENCE TO 05 PIXEL 3SIGMA EVERY WHERE ON THE WAFER), which is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates generally to semiconductor wafer fabrication and metrology, and more particularly to a method and system for aligning semiconductor device reference and test images. Background technique [0004] Fabricating semiconductor devices, such as logic and memory devices, typically involves processing the semiconductor devices using a number of semiconductor fabrication and metrology processes to form the various featur...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66H01L21/67
CPCG06T7/001G06T7/30G06T2207/20021G06T2207/30148G06V10/7515G06V2201/06H01L22/34H01L22/12H01L22/24H01L22/26H01L21/67242G06T7/74G06T7/33
Inventor 陈宏M·库克P·库马尔K·吴
Owner KLA CORP