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Groove-type device and preparation method thereof

A trench type and device technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of potential difference increase and electric field enhancement near the bottom of the trench, so as to enhance the carrier injection effect and manufacture The effect of small process changes and reduced conduction loss

Pending Publication Date: 2020-07-03
成都森未科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Although the increase of the trench depth can effectively reduce the operating loss of the device, in the traditional trench gate structure, the electrodes inside the trench will also increase with the increase of the trench depth, resulting in an increase in the potential difference near the bottom of the trench. The electric field on the sidewalls of the trench is enhanced, this effect will limit the increase of the trench depth

Method used

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  • Groove-type device and preparation method thereof
  • Groove-type device and preparation method thereof
  • Groove-type device and preparation method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0040] A trench type device includes a substrate 101, a body region 201 is disposed on the substrate 101, a second conductive layer 501 is disposed on the body region 201, and a first insulating layer 501 is disposed in the second conductive layer 501. A dielectric layer 301, a gate dielectric layer 302 is arranged under the first insulating dielectric layer 301, a second insulating dielectric layer 303 is arranged under the gate dielectric layer 302, the first insulating dielectric layer 301, the gate dielectric layer 302 and the first insulating dielectric layer 302 The two insulating dielectric layers 303 are connected, the gate dielectric layer 302 is located in the body region 201, the second insulating dielectric layer 303 is located in the substrate 101, and the gate dielectric layer 302 and the second insulating dielectric layer 303 are provided with The first conductive layer 401 , the depth of the first conductive layer 401 is not less than the depth of the body regio...

Embodiment 2

[0048] A method for preparing a grooved device, comprising the steps of:

[0049] Step 1: growing a field oxide layer on the substrate 101, not limited to the silicon substrate 101, such as image 3 shown;

[0050] Step 2: using a photolithography plate to expose part of the field oxide layer and etch it away to expose the substrate 101, such as Figure 4 shown;

[0051] Step 3: performing trench etching on the exposed substrate 101, such as Figure 5 shown;

[0052] Step 4: Deposit to obtain the second insulating dielectric layer 303, such as Figure 6 shown;

[0053] Step 5: Etching part of the aforementioned second insulating dielectric layer 303, and retaining part around and at the bottom of the trench, such as Figure 7 shown;

[0054] Step 6: growing the gate dielectric layer 302 on the side walls of the trench and the upper surface of the substrate 101, such as Figure 8 shown;

[0055] Step 7: Deposit to obtain the first conductive layer 401, such as Figure 9...

Embodiment 3

[0060] A trench type device includes a substrate 101, a body region 201 is disposed on the substrate 101, a second conductive layer 501 is disposed on the body region 201, and a first insulating layer 501 is disposed in the second conductive layer 501. A dielectric layer 301, a gate dielectric layer 302 is arranged under the first insulating dielectric layer 301, a second insulating dielectric layer 303 is arranged under the gate dielectric layer 302, the first insulating dielectric layer 301, the gate dielectric layer 302 and the first insulating dielectric layer 302 The two insulating dielectric layers 303 are connected, the gate dielectric layer 302 is located in the body region 201, the second insulating dielectric layer 303 is located in the substrate 101, and the gate dielectric layer 302 and the second insulating dielectric layer 303 are provided with The first conductive layer 401 , the depth of the first conductive layer 401 is not less than the depth of the body regio...

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Abstract

The invention relates to the field of semiconductor manufacturing, and especially relates to a groove-type device and a preparation method thereof. The device comprises a substrate, wherein a body region is arranged on the substrate. A second conductive layer is arranged on the body region. A first insulating dielectric layer is arranged in the second conductive layer. A gate dielectric layer is arranged below the first insulating dielectric layer. A second insulating dielectric layer is arranged below the gate dielectric layer. The first insulating dielectric layer, the gate dielectric layerand the second insulating dielectric layer are communicated. The gate dielectric layer is located in the body region, the second insulating dielectric layer is located in the substrate, a first conductive layer is arranged in the gate dielectric layer and the second insulating dielectric layer, and the depth of the first conductive layer is not smaller than that of the body region. In the structure of the invention, the depth of the gate electrode in the trench can be different from the depth of the trench. When the structure is applied to IGBT design, the carrier injection effect can be enhanced, and the conduction loss of the IGBT can be reduced.

Description

technical field [0001] The present application relates to the field of semiconductor manufacturing, in particular to a trench device and a preparation method thereof. Background technique [0002] During the development of voltage-controlled power semiconductor devices, trenches were introduced in order to achieve higher current densities on smaller chips. Both research and practice have proved that the depth of the trench can change the carrier concentration distribution of the device in the on state. Such devices include power MOS, IGBT and so on. The following is an example of 600V200A IGBT, such as figure 2 As shown, the active area depth is fixed at 11um, the groove width is fixed at 1.5um, and the groove depths are changed to 5um, 10um, and 15um respectively. However, the research results show that with the increase of the trench depth, the distribution of internal carriers is as follows: Figure 11 As shown, especially the charge accumulation on the outer wall of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/423H01L29/739H01L29/78H01L21/28H01L21/336H01L21/331
CPCH01L29/7827H01L29/7397H01L29/401H01L29/4236H01L29/42364H01L29/66045H01L29/66037H01L29/66068H01L29/66666H01L29/66348
Inventor 胡强金涛秦潇峰王思亮蒋兴莉
Owner 成都森未科技有限公司