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Low dropout voltage regulator and related method

A low-drop voltage regulator and voltage technology, which is applied in the direction of instruments, adjustment of electrical variables, and output power conversion devices, etc., can solve the problems of increased circuit area and increased power consumption

Active Publication Date: 2020-07-14
NOVATEK MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

LDOs in the prior art can include power transistors with larger dimensions, but this results in an increase in circuit area
LDOs in the prior art can always increase the current flowing through the power transistor, but it will lead to an increase in power consumption
The LDO in the prior art can enlarge the load capacitance connected to the SAR ADC, but the circuit area also increases

Method used

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  • Low dropout voltage regulator and related method
  • Low dropout voltage regulator and related method
  • Low dropout voltage regulator and related method

Examples

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Embodiment Construction

[0045] Figure 7 is a schematic diagram of a low dropout voltage regulator 70 in the prior art. LDO 70 includes a power transistor M7 and an operational amplifier OP, wherein a current I LDO7 Flow through power transistor M7. The low dropout voltage regulator 70 is coupled to a load circuit 16 and used to provide an output voltage V to the load circuit 16 LDO7 . output voltage V LDO7 It is expected to be a stable direct current (DC) voltage. The load circuit 16 receives a clock signal CLK and sinks a current I from the low dropout regulator 10 sink . In one embodiment, the load circuit 16 may be a SAR ADC. clock signal CLK and sink current I sink timing diagram, such as Figure 8 shown. clock signal CLK at low clock voltage V CL with high clock voltage V CH alternate between, wherein, in a first half-period T1, the clock signal CLK remains at a low clock voltage V CL , and in a second half period T2, the clock signal CLK remains at a high clock voltage V CH . Su...

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Abstract

A low dropout voltage regulator, coupled to a load circuit receiving a clock signal, includes an amplifier; a power transistor comprising a control terminal, coupled to an output terminal of the amplifier; and a first terminal, coupled to a positive input terminal of the amplifier and the load circuit; and a control circuit, configured to control a current flowing through the power transistor in response to the clock signal.

Description

technical field [0001] The present invention relates to a low dropout voltage regulator (Low Dropout Voltage Regulator, LDO) and a related method, in particular to a low dropout voltage regulator and a related method, which can suppress the output of the low dropout voltage regulator through a clock-based circuit Voltage ripple (Ripple). Background technique [0002] The so-called clock-based circuit suppression refers to, such as successive approximation register analog-to-digital converter (Successive Approximation Register Analog-to-digital Converter, SAR ADC), flash memory analog-to-digital converter (Analog-to-digital Converter, ADC), switch-based amplifier , and has low power consumption characteristics. For example, successive approximation register analog-to-digital converters have been widely used in various applications. For energy issues, the SAR ADC can be powered by a relatively low DC (direct current) voltage. A low-dropout regulator is used to power the suc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05F1/56
CPCG05F1/561G05F1/575H03M1/0845H03M1/38H02M1/14H03M1/0604
Inventor 郭亮廷陈慕蓉廖祈钧
Owner NOVATEK MICROELECTRONICS CORP
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