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Convolution operation device and method based on memristor

A convolution operation and memristor technology, applied in the field of signal processing, can solve the problems of low operation speed, consume software and hardware overhead, reduce operation speed, etc., and achieve the effect of improving speed and saving software and hardware overhead.

Inactive Publication Date: 2020-07-17
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The existing convolution operation circuit based on the memristor array has two deficiencies: first, the receptive field sequentially slides over the input image is a serial process, resulting in low operation speed; second, the convolution kernel involved in the multiplication and addition operation, The input image is usually a two-dimensional matrix, which must be converted into a one-dimensional vector in advance. This process requires a certain amount of software and hardware overhead, and will also reduce the calculation speed.

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  • Convolution operation device and method based on memristor
  • Convolution operation device and method based on memristor

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Embodiment 1

[0036] as attached figure 1 and 2 As shown, in this embodiment, m=n=8, a=b=3, k=j=6, the convolution step s in the row direction is 1, and the convolution step t in the column direction is 1. A memristor-based convolution operation device provided in this embodiment includes a memristor chip, and the memristor chip includes a plurality of memristor arrays, where a plurality of memristor arrays refers to more than or equal to 36 memristor array. Each memristor array is used to store a convolution kernel, as attached figure 1 As shown, the convolution kernel is a 3×3 matrix, and the memristor array includes memristors in 3 rows and 3 columns. Assume that the input signal array is an 8×8 matrix, as shown in the attached figure 2 As shown in the middle and upper panels; set the row direction convolution step size s to 1, and the column direction convolution step size t to 1, then the memristor chip includes [(8-3) / 1+1]×[(8 -3) / 1+1] memristor arrays, as attached figure 2 As...

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Abstract

The invention discloses a memristor-based convolution operation device, which comprises a memristor chip that is characterized by comprising x*y memristor arrays, wherein each memristor array comprises a rows and b columns of memristors, and the memristor arrays are used for storing convolution kernels; when the m rows and n columns of input signal arrays are transmitted to the memristor chip, theinput signal arrays and the k*j memristor arrays are subjected to convolution operation at the same time, and k rows and j columns of output signal arrays are obtained; wherein k = (m-a) / s+1, and j =(n-b) / t+1; s and t respectively represent convolution step lengths in the row direction and the column direction in convolution operation, and x*y is greater than or equal to k*j. According to the memristor-based convolution operation device and method provided by the invention, the two-dimensional memristor array is used, so that the convolution operation is changed into a parallel process, theconversion of a convolution kernel and an input image from a two-dimensional matrix to a one-dimensional vector is omitted, and the speed of the convolution operation is improved.

Description

technical field [0001] The invention relates to the field of signal processing, in particular to a memristor-based convolution operation device and method. Background technique [0002] At present, the convolution operation based on the memristor array is a research hotspot in academia. Convolution operation is an important part of various image processing algorithms and neural network algorithms. Assuming that the size of the two-dimensional convolution kernel is a×b, the execution process of the convolution algorithm on the two-dimensional image signal is as follows: a size is a×b The rectangular receptive field of b slides over the entire input image in turn, and at each position of the slide, the image data within the receptive field is multiplied by the corresponding elements in the convolution kernel to obtain a×b products, which a×b The product is added to obtain the value of the corresponding position element of the output feature map. Traditional digital logic cir...

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Application Information

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IPC IPC(8): G06N3/04
CPCG06N3/045
Inventor 郭令仪段杰斌李琛沈灵
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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