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Method for improving utilization rate of wafer probe station

A technology of probe station and utilization rate, which is applied in the direction of electrical components, electric solid-state devices, circuits, etc., can solve the problems of reduced utilization rate of wafer test machines, incompatibility with traditional wafer testing, and increased cost of wafer testing, etc. Achieve the effects of reducing the risk of wafer damage, preventing wafer warping, and improving strength

Active Publication Date: 2020-07-28
SIEN QINGDAO INTEGRATED CIRCUITS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method of changing the chuck involves equipment modification, which will inevitably increase the test cost, and it cannot be restored at zero cost after the modification, so it cannot be compatible with testing traditional wafers
As a result, the utilization rate of wafer testing equipment is reduced, and the cost of wafer testing is increased

Method used

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  • Method for improving utilization rate of wafer probe station
  • Method for improving utilization rate of wafer probe station
  • Method for improving utilization rate of wafer probe station

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0067] In order to overcome the problems of low utilization rate of wafer testing machine and increased test cost in the prior art, this embodiment provides a method for improving the utilization rate of wafer probe station, such as image 3 As shown, the method includes the following steps:

[0068] A wafer is provided, including a front side of the wafer and a back side of the wafer, and the wafer is subjected to back grinding and thinning treatment and back gold treatment;

[0069] A metal patch is attached to at least a partial area of ​​the back of the wafer, and the center of the metal patch coincides with the center of the wafer; wherein, the back of the wafer to which the metal patch is attached presents a plane as a whole Mode;

[0070] placing the wafer attached with the metal patch on the probe station for testing.

[0071] In a preferred embodiment of this embodiment, the metal patch includes a disc-shaped metal patch, and the metal patch is selected from any one...

Embodiment 2

[0083] This embodiment also provides a method for improving the utilization rate of the wafer probe station, and the similarities with Embodiment 1 will not be repeated, and the difference lies in:

[0084] In this example, if Figure 7 As shown, the provided wafer 70 includes a wafer front 701 and a wafer back 702. The non-taiko process is used to grind and thin the wafer back 702 to the required thickness. The wafer back 702 is attached with a metal sticker Sheet 704. In this embodiment, the metal patch 704 covers the entire wafer backside 702 , the diameter of the metal patch is between 200 mm and 300 mm, and the thickness of the metal patch is between 0.3 mm and 0.8 mm.

[0085] In a further embodiment of this embodiment, the wafer 70 includes 8" and 12" wafers, and in the 8" wafer 70, the diameter of the metal patch 704 is about 200 mm, and the thickness is between 0.3 mm˜0.8 mm. In the 12” wafer 70 , the metal patch 704 has a diameter of about 300 mm and a thickness of...

Embodiment 3

[0090] This embodiment also provides a method for improving the utilization rate of the wafer probe station, and the similarities with Embodiment 1 or 2 will not be repeated, and the difference lies in:

[0091] After the test is completed, the wafer attached with the metal patch is cut and packaged.

[0092] Before the wafer is cut and packaged, the backside grinding and thinning of the wafer attached with the metal patch can also be performed.

[0093] In a preferred embodiment of this embodiment, as Figure 8 As shown, the wafer can be diced together with the metal patch on its back to form independent dies 30 , and then the independent dies 30 can be packaged.

[0094] In another preferred embodiment of this embodiment, with Figure 7 The wafer shown is taken as an example, and the wafer and the metal patch 704 on the back of the wafer are cut. However, in this preferred embodiment, the wafer and the metal patch 704 are cut in the form of a combination of multiple crysta...

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Abstract

The invention provides a method for improving the utilization rate of a wafer probe station. The method comprises the steps providing a wafer which comprises a wafer front surface and a wafer back surface, and carrying out back surface grinding and thinning and back gold processing on the wafer; attaching a metal patch to at least part of the area of the back surface of the wafer, wherein the center of the metal patch coincides with the center of the wafer, the whole back surface of the wafer attached with the metal patch is planar; and placing the wafer attached with the metal patch on a probe station for testing. After the metal patch is attached to the back surface of the wafer, the whole wafer is planar, the wafer can be tested on a traditional testing machine table, the utilization rate of the testing machine table is increased, and the wafer testing cost is reduced. After the test is completed, the subsequent cutting and packaging process can be carried out without removing the metal patch. The method provided by the invention does not pollute the environment of the test stage, and is suitable for subsequent cutting and packaging processes at the same time.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to the field of semiconductor power device testing, and more specifically to a method for improving the utilization rate of a wafer probe station. Background technique [0002] In integrated circuits, semiconductor devices, especially power devices, are an important field of application. In the manufacturing process of power devices, the backside process of the wafer has an important impact on the reduction of device resistance and subsequent packaging. As for the grinding process of the backside process, there are mainly Taiko process and traditional non-Taiko (non-Taiko) grinding process in the prior art. When the wafer is ground by the Taiko process, the outer edge of the wafer will be kept, and only the inside of the wafer will be ground and thinned. This process can reduce the handling risk of thin wafers, and can reduce the warpage of wafers caused by traditional...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66H01L23/00
CPCH01L22/10H01L22/30H01L23/562
Inventor 郭海涛严大生蔡育源徐传贤司徒道海
Owner SIEN QINGDAO INTEGRATED CIRCUITS CO LTD