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P-type MOSFET and manufacturing method thereof

A manufacturing method, N-type technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of large fluctuations in phosphorus ion implantation depth and large influence on device threshold voltage, so as to improve device performance and product quality Yield, the effect of reducing local fluctuations

Pending Publication Date: 2020-08-28
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the prior art, the N well is usually implemented by implanting a layer of phosphorus ions. The depth of phosphorus ion implantation fluctuates greatly, which has a great impact on the threshold voltage of the device.

Method used

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  • P-type MOSFET and manufacturing method thereof
  • P-type MOSFET and manufacturing method thereof
  • P-type MOSFET and manufacturing method thereof

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Embodiment Construction

[0064] The structural reference of the channel region of the P-type MOSFET in the embodiment of the present invention Figure 1K and Figure 1L As shown, the channel region is composed of an N well 8 covered by a gate structure, and the N well 8 includes a first implanted region 4, a second implanted region 5 and a third implanted region 6 formed in the semiconductor substrate 101. The superposition region 7 is formed and the superposition region 7 is annealed, that is, the N well 8 is formed after the superposition region 7 is annealed. The semiconductor substrate 101 please refer to Figure 1A as shown, Figure 1K Only the structure of the N-type deep well 2 formed in the semiconductor substrate 101 is illustrated in FIG.

[0065] In the embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.

[0066] Preferably, a field oxide layer 1 is formed on the semiconductor substrate 101, and the active region is isolated by the field ox...

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PUM

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Abstract

The invention discloses a P-type MOSFET, which is characterized in that a channel region is composed of an N well covered by a gate structure, the N well comprises a superposition region composed of afirst implantation region, a second implantation region and a third implantation region, and the superposition region is subjected to annealing treatment; the implantation impurities of the first tothird implantation regions are phosphorus, xenon and arsenic respectively; the doping concentration of the third implantation region is used for adjusting the threshold voltage, the ion implantation process of the third implantation region is carried out after the ion implantation process of the second implantation region is completed, and the second implantation region forms an amorphous layer ina semiconductor substrate so as to enable the arsenic implantation of the third implantation region to be uniform. The invention further discloses a manufacturing method of the P-type MOSFET. According to the invention, the local fluctuation of the threshold voltage can be reduced, and the device performance and the product yield are improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a P-type MOSFET. The invention also relates to a manufacturing method of the P-type MOSFET. Background technique [0002] A P-type MOSFET, that is, a PMOS, is usually formed in an N-type deep well (Deep Nwell layer, DNW), and a channel region is formed by using an N well. The ion implantation process of the N-type deep well is generally placed before the ion implantation process of the N well. The implantation energy of the ion implantation process of the N-type deep well is large, and the implantation depth is deep. Before the ion implantation of the N-type deep well, it is usually necessary to form a pad oxide layer on the surface of a semiconductor substrate such as a silicon substrate, and the ion implantation of the N-type deep well will pass through the pad oxide layer. [0003] However, after the ion implantation process of the N-type deep w...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06H01L29/10H01L29/36H01L29/167H01L21/336
CPCH01L29/78H01L29/7838H01L29/0607H01L29/0684H01L29/1054H01L29/36H01L29/167H01L29/66477
Inventor 李中华
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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