P-type MOSFET and manufacturing method thereof
A manufacturing method, N-type technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of large fluctuations in phosphorus ion implantation depth and large influence on device threshold voltage, so as to improve device performance and product quality Yield, the effect of reducing local fluctuations
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[0064] The structural reference of the channel region of the P-type MOSFET in the embodiment of the present invention Figure 1K and Figure 1L As shown, the channel region is composed of an N well 8 covered by a gate structure, and the N well 8 includes a first implanted region 4, a second implanted region 5 and a third implanted region 6 formed in the semiconductor substrate 101. The superposition region 7 is formed and the superposition region 7 is annealed, that is, the N well 8 is formed after the superposition region 7 is annealed. The semiconductor substrate 101 please refer to Figure 1A as shown, Figure 1K Only the structure of the N-type deep well 2 formed in the semiconductor substrate 101 is illustrated in FIG.
[0065] In the embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.
[0066] Preferably, a field oxide layer 1 is formed on the semiconductor substrate 101, and the active region is isolated by the field ox...
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