Simulation method for power added efficiency of LDMOS power amplifier
A power-added efficiency and power amplifier technology, which is applied to power amplifiers, improved amplifiers to improve efficiency, etc., can solve problems such as low precision and complexity, and achieve the effects of reducing design times, reducing differences, and improving simulation accuracy
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0073] For the two RF power LDMOS chips, the process steps are different and the structures are different. The device names are L0009_2507 and L0009_2508, and the codes are S1 and S2 respectively. Utilize the technical scheme simulation of the present invention to obtain the steps of the RF power amplifier power-added efficiency that above-mentioned two kinds of devices build are as follows:
[0074] Step 1. Obtain the DC and AC small-signal test data of the LDMOS device, use the analytical method to build a DC equivalent electrical characteristic model, and combine the small-signal S-parameter test data of the LDMOS device to build an AC small-signal equivalent electrical characteristic model;
[0075] Step 2, according to the bias condition of the power amplifier, determine the bias voltage corresponding to the two devices S1 and S2 under the fixed bias current condition;
[0076] Step 3. Taking the S1 device as an example, conduct source-pull and load-pull simulations on th...
Embodiment 2
[0083] In this example, the method of the present invention is combined with TCAD simulation software, and the structure of the LDMOS device is optimized by means of co-simulation. Such as Figure 9 , 10 as shown, Figure 9 It is a schematic diagram of the original LDMOS device structure, including semiconductor substrate 1, source extension region 2, source region 3, channel region 4, gate oxide 5, gate 6, drift region 7 and drain region 8, and Figure 10 It is a schematic diagram of the improved LDMOS device structure, including semiconductor substrate 1, source extension region 2, source region 3, channel region 4, gate oxide 5, gate 6, drift region 7, drain region 8, lightly doped drift region 9. Comparing the two device structures, it can be seen that the improved LDMOS device structure ( Figure 10 ) introduces a lightly doped drift region 9, and the doping concentration and size of other parts are the same as Figure 9 be consistent. Among them, the introduction of...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More