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Soc chip performance and power consumption optimization method and device, equipment and medium

A chip performance and optimization method technology, applied in the computer field, can solve the problems of long sampling period, difficult adjustment of threshold value, high cost of load calculation, etc., to achieve precise control of performance and power consumption, save power consumption, and meet needs Effect

Active Publication Date: 2020-09-01
FUZHOU ROCKCHIP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] 1. The threshold value is not easy to adjust: For different application scenarios, the required performance is different, so the threshold value cannot be used universally and needs to be adjusted according to the scenario, and this adjustment process is very cumbersome, too high will lead to waste of power consumption, too high If it is low, the performance is not enough. The most troublesome thing is that the performance requirements of some scenes are not fixed, such as game rendering, some complex scenes require higher performance, and some simple scenes can be satisfied with lower performance
[0004] 2. The load sampling period is not easy to adjust: the sampling period is too long to adjust the performance and power consumption in time. Conversely, if the period is too short, the cost of load calculation is too high
[0005] 3. Lack of precise adjustment capability: The current load sampling is usually the entire system, including other tasks and other functions that we don’t care about, so the power consumption cannot be minimized

Method used

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  • Soc chip performance and power consumption optimization method and device, equipment and medium
  • Soc chip performance and power consumption optimization method and device, equipment and medium
  • Soc chip performance and power consumption optimization method and device, equipment and medium

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0035] This embodiment provides a method for optimizing Soc chip performance and power consumption, such as Figure 1 to Figure 3 shown, including:

[0036] Step S1. Different upper-layer applications register a key area respectively, and provide the expected time-consuming threshold value o of the key area and the list of hardware resources hw_list used (such as cpu, gpu, vpu, etc.). The key area in the present invention refers to: in an application program or a usage scenario, the area where the performance or power consumption is most concerned.

[0037] For example: an application can mark the drawing function as a key area, and expect to maintain a refresh performance of 60fps, then it can set the expected time-consuming threshold of the key area to o=16.6ms, and then its drawing process uses cpu and gpu , you can add these two pieces of hardware to the list of registered hardware resources, and finally mark the start and end of the key area at the start and end of the d...

Embodiment 2

[0052] In this embodiment, a device is provided, such as image 3 As shown, including: a device for optimizing Soc chip performance and power consumption, including

[0053] The obtaining module is used to obtain the expected time-consuming threshold value o of the key area provided by the upper-layer application and the list of hardware resources used after registering a key area respectively in different upper-layer applications;

[0054] The marking module is used to set the start function for calling the key area at the starting position of the key area, and set the call end function for calling the key area at the end position;

[0055] The statistical module is used to traverse the corresponding hardware resource list after the key area corresponding to the upper application is started, and count the time-consuming t of the key area and the duty cycle i1, i2...in of each hardware in the hardware resource list, through the formula rn= t*in calculates the running time r1,...

Embodiment 3

[0067] This embodiment provides an electronic device, such as Figure 4 As shown, it includes a memory, a processor, and a computer program stored in the memory and operable on the processor. When the processor executes the computer program, any implementation manner in Embodiment 1 can be realized.

[0068] Since the electronic device introduced in this embodiment is the device used to implement the method in Embodiment 1 of this application, based on the method described in Embodiment 1 of this application, those skilled in the art can understand the electronic device of this embodiment. Specific implementation methods and various variations thereof, so how the electronic device implements the method in the embodiment of the present application will not be described in detail here. As long as a person skilled in the art implements the equipment used by the method in the embodiment of the present application, it all belongs to the protection scope of the present application. ...

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PUM

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Abstract

The invention provides an Soc chip performance and power consumption optimization method and device, equipment and a medium, and the method comprises the steps: enabling an upper-layer application toregister a key region, and providing an expected time consumption threshold value o of the key region and a used hardware resource list; after the key areas are started, traversing the hardware resource list, counting the consumed time t of the key areas, calculating the running time rn of each piece of hardware, acquiring the consumed time t of the previous j statistical key areas, and performingweighted averaging to obtain weighted consumed time T; wherein if T is greater than o, it is indicated that the performance is insufficient, finding out the hardware with the maximum running time rn,and improving the performance of the hardware by one gear, and otherwise, if T is greater than o, indicating that the performance is sufficient, finding out the hardware with the minimum running timern, and lowering the performance of the hardware by one gear. Therefore, adjustment can be carried out according to the operation characteristics of the key hardware resources when the upper-layer application operates, accurate control performance and power consumption of a specific application scene are achieved, requirements can be met, and power consumption can be saved.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a Soc chip performance and power consumption optimization method, device, equipment and medium. Background technique [0002] For Soc chips, performance and power consumption are contradictory, because the main way to improve performance is to increase frequency, which often requires synchronous increase in voltage to ensure stability. At this time, both static and dynamic power consumption will increase; and power consumption control just Instead, voltage and frequency need to be reduced. If you want to balance performance and power consumption, you can only make dynamic adjustments. At present, the main adjustment solution is to adjust according to the load. The driver performs regular sampling of hardware resources such as cpu / vpu / gpu to calculate the load per unit time (that is, accounted for Duty ratio), when the load is lower than a certain threshold value, the p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78G06F9/50
CPCG06F15/7807G06F9/5094Y02D10/00
Inventor 陈谋春
Owner FUZHOU ROCKCHIP SEMICON