Port configurable router design method based on wide-port heterogeneous tiles and router

Abstract

The invention discloses a port configurable router design method based on wide-port heterogeneous tiles and a router. The design method comprises the steps: determining the highest port bandwidth andthe number of ports of the router; designing a hardware communication protocol stack, and determining the number of initially bound lanes of each physical coding sub-layer module; according to the specified clock frequency, determining the width of the internal exchange data of the router for matching the highest bandwidth of the port; determining the number of internal switching ports according to the total bandwidth of the chip pins; and designing an internal switching component of the router based on the heterogeneous tiles, and performing butt joint on the obtained hardware communication protocol stack and the internal switching component of the router to finally obtain the router with the configurable port. According to the invention, the high-order routers can be flexibly organized into a plurality of heterogeneous wide-port low-order tile arrays which are easy to realize by hardware according to rear-end chip area constraints and communication bandwidth requirements, and the number and bandwidth of router ports are configurable.

Description

technical field [0001] The present invention mainly relates to high-level routers oriented to high-performance computing HPC (High Performance Computing), and specifically relates to a design method of a port-configurable router based on wide-port heterogeneous tiles and a router. The router is flexibly organized into multiple heterogeneous tile arrays and the number of ports is configurable. Background technique [0002] The interconnection communication network is the most important infrastructure of HPC, which realizes the interconnection of computing nodes and I / O nodes, and carries the message and data communication between all nodes. The latency and bandwidth of remote storage access between computing nodes mainly depends on the latency and bandwidth of the interconnection network. As the parallel scale continues to increase, the performance of HPC depends more and more on the efficiency of data communication between huge computing resources rather than computing perf...

AI Technical Summary

Problems solved by technology

The dilemma of Moore's Law has brought two impacts on the design of high-end router chips: 1) Under the constraint of the limited number of high-speed I / O pins, the total bandwidth of router chips remains constant. To increase the density of router ports, the port bandwidth needs to be reduced; 2) ) The difficulty in the design of high-level routers is the low-latency, high-throughput packet hardware scheduling circuit, and its design complexity is O(N 2 ), when the clock frequency remains unchanged, in order to match the higher port bandwidth, the router needs to process more packets per unit clock cycle, which puts forward higher requirements for its arbitration logic complexity and power consumption

Compared with more than ten years ago, the design of high-end router chips is more difficult to meet the requirements of high bandwidth and low latency in addition to the technical challenges of scalability, reliability and power consumption.

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