Chip package structure and manufacturing method thereof
A technology of chip packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve problems such as uneven force, electrical bonding failure, and poor reliability of chip packaging structure. Achieve the effect of improving reliability, reducing uneven force, and reducing the possible effect of electrical joint failure
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[0033] Figure 1A to Figure 1D It is a schematic cross-sectional view of a manufacturing process of a chip package structure 100 according to an embodiment of the present invention. Please refer to Figure 1A , First, the circuit substrate 110 and the chip 120 are provided. In detail, the circuit substrate has a plurality of pads 112 and a solder mask 114. The solder mask 114 covers the conductive circuits (not shown) in the circuit substrate 110 and exposes a plurality of pads 112 to facilitate subsequent electrical connections of the pads 112. The chip 120 has an active surface 120a. The chip 120 is, for example, a memory chip, a microprocessor chip, or an application-specific integrated circuit chip (ASIC). However, the invention does not limit the type of the chip 120, and may be determined according to actual design requirements.
[0034] Please continue to refer Figure 1A , The circuit substrate 110 is formed with a two-stage thermosetting adhesive layer 130. The two-sta...
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