Intrinsic Linear Phase Interpolator

Abstract

The present invention provides an intrinsic linear phase interpolator, including a phase interpolation module, a first constant current source module and a second constant current source module, the phase interpolation module includes a first capacitor group and a second capacitor group, the The first constant current source module is used to charge or discharge the first capacitor bank with a constant current, and the second constant current source module is used to charge or discharge the second capacitor bank with a constant current. The intrinsic linear phase interpolator includes a first constant current source module and a second constant current source module, the first constant current source module is used to charge or discharge the first capacitor bank with a constant current, so The second constant current source module is used to charge or discharge the second capacitor bank with a constant current, so that the charging and discharging process of the first capacitor bank and the second capacitor bank on the intrinsic or mathematical expression The medium current change is linear to optimize the phase and reduce the introduction of spurs.

Description

technical field [0001] The invention relates to the technical field of phase-locked loops, in particular to an intrinsic linear phase interpolator. Background technique [0002] The quantization noise introduced by the Sigma-Delta Modulator (SDM) in the Fractional-N PLL will bring jitter to the output clock. Among them, the fractional divider (Fractional Divider) implemented by the intrinsic linear phase interpolator (Phase interpolator) can effectively reduce the quantization noise, but in the process of charging and discharging the capacitor of the intrinsic linear phase interpolator, the nonlinear change of the current magnitude will be degrade phase noise or introduce spurs. [0003] Therefore, it is necessary to provide a novel intrinsic linear phase interpolator to solve the above-mentioned problems in the prior art. Contents of the invention [0004] The purpose of the present invention is to provide an intrinsic linear phase interpolator, which realizes the linea...

AI Technical Summary

Problems solved by technology

[0002] The quantization noise introduced by the Sigma-Delta Modulator (SDM) in the Fractional-N PLL will bring jitter to the output clock

Among them, the fractional divider (Fractional Divider) implemented by the intrinsic linear phase interpolator (Phase interpolator) can effectively reduce the quantization noise, but in the process of charging and discharging the capacitor of the intrinsic linear phase interpolator, the nonlinear change of the current magnitude will be degrade phase noise or introduce spurs

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