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A three-dimensional integrated circuit layout method based on through-silicon vias

A technology of integrated circuits and layout methods, applied in the field of three-dimensional integrated circuit layout based on through-silicon vias, can solve problems such as the length of interconnecting lines, and achieve the effects of uniform density, improved effective utilization, and short line lengths

Active Publication Date: 2022-01-04
SOUTHWEAT UNIV OF SCI & TECH
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

Compared with the previous method, this method has a significant improvement in the number of TSVs. However, because TSVs are not actually placed in the layout, it does not affect the length of the interconnection line, so the length of the interconnection line is relatively long.

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Embodiment Construction

[0027] In order to make the objects, technical solutions and advantages of the present invention, the present invention is further illustrated in connection with the accompanying drawings.

[0028] In this embodiment, see Figure 1-7 As shown, the present invention proposes a three-dimensional integrated circuit layout method based on a silicon via, comprising the steps:

[0029] The first step is to mix the three-dimensional layout of the circuit, obtain a coarse layer of layered, while generating silicon vent;

[0030] In the second step, the mixed two-dimensional layout is performed according to the results of the mixed three-dimensional layout, and the precise layout results are obtained;

[0031] In the third step, based on the result of the result, the macro unit is legally determined, reducing the overlapping of the macro unit and other units, and then secures the macro unit;

[0032] In the fourth step, a three-dimensional layout is performed on the standard unit;

[0033] ...

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Abstract

The invention discloses a three-dimensional integrated circuit layout method based on through-silicon vias. The result of mixed two-dimensional layout, to obtain accurate layout results; the third step, according to the obtained accurate layout results, legalize the macrocells, reduce the overlap between the macrocells and other cells, and then fix the macrocells; the fourth step, Three-dimensional layout of standard cells; fifth step, two-dimensional layout of standard cells; sixth step, complete detailed layout of three-dimensional integrated circuits, and obtain the final optimized layout results. In the physical design of the chip, the present invention adopts a better layout algorithm to obtain a smaller number of through-silicon holes, improve the performance of the chip, and also improve the production efficiency of the chip.

Description

Technical field [0001] The present invention belongs to the technical field of circuit layout, and more particularly to a three-dimensional integrated circuit layout method based on a silicon vent. Background technique [0002] The three-dimensional integrated circuit is one of the ideal solutions for overcoming modern and next-generation integrated circuits. At the same time, the three-dimensional integrated circuit can effectively reduce the interconnect length and improve the circuit performance. However, silicon vent is a key technique in a three-dimensional integrated circuit, which is used to connect different layers in three-dimensional integrated circuits, and there are many problems. Under the current technique, the silicon vent is very large relative to the interconnect metal line. Therefore, a large number of silicon via will occupy a large silicon area, resulting in the final chip yield. Additionally, the silicon vent is usually occupying a blank block between a stand...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
CPCH01L21/76898
Inventor 俞文心程鑫李镰江江宁何刚刘畅
Owner SOUTHWEAT UNIV OF SCI & TECH