Semiconductor storage element and manufacturing method thereof

Abstract

The invention provides a semiconductor storage element and a manufacturing method thereof. The semiconductor storage element comprises a substrate, an isolation structure, a first gate dielectric layer, a first conductor layer, a second gate dielectric layer, a second conductor layer and a protective layer. The substrate has an array region and a peripheral region. The isolation structure is disposed in the substrate between the array region and the peripheral region. The first gate dielectric layer is disposed on the substrate of the array region. The first conductor layer is disposed on thefirst gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the peripheral region. The second conductor layer is disposed on the second gate dielectric layer. The second conductor layer extends to cover a part of the top surface of the isolation structure. The protective layer is disposed between the second conductor layer and the isolation structure.

Description

technical field [0001] The invention relates to an integrated circuit and a manufacturing method thereof, in particular to a semiconductor storage element and a manufacturing method thereof. Background technique [0002] With the rapid development of technology, in order to reduce the cost and simplify the process steps of semiconductor components, it has gradually become a trend to integrate the components of the cell array region and the peripheral region on the same chip. [0003] In conventional processes, different gate structures in the cell array region and the peripheral region need to be defined using different photomasks. However, the isolation structure between the cell array area and the peripheral area will undergo multiple etching processes, resulting in excessive loss of the isolation structure. In this case, the conductor layer on the isolation structure in the peripheral area close to the boundary area will also be lost, causing poly residue defects to occu...

AI Technical Summary

Problems solved by technology

However, the isolation structure between the cell array area and the peripheral area will undergo multiple etching processes, resulting in excessive loss of the isolation structure

In this case, the conductor layer on the isolation structure in the peripheral area close to the boundary area will also be lost, resulting in the generation of poly residue defects, thereby reducing the reliability and yield of the device.

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