Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The device comprises a substrate, an epitaxial layer, a source end region, a drain end region, a gate structure and aside wall, wherein the source end region comprises a P-type well region, at least one first injection region, at least one second injection region, a first shallow doped region, a second shallow doped region, and a third injection region which is formed in the whole source region and covers all the first injection region, the second injection region, a first shallow doping region and a second shallow doping region, the third injection region is an N-type injection region, and the doping concentration of the third injection region is larger than that of the first shallow doping region and thatof the second shallow doping region and smaller than that of the first injection region and that of the second injection region. The device is advantaged in that the N-type injection region of whichthe concentration is higher than that of the shallow doped region is added in a source end region, so the on resistance between a source end and a drain end is effectively reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] With the wide application of Lateral Double Diffused MOS Transicor (LDMOS) in integrated circuits, the performance requirements for LDMOS are also getting higher and higher, such as generally requiring devices to have a higher turn-off breakdown voltage (off -BV) and lower on-resistance (Rdson). [0003] Generally speaking, the way to reduce the on-resistance of LDMOS devices is to continuously increase the concentration of the drift region and at the same time, through various RESURF (Reduced SURface Field, reduce the surface battery) theories, so that it can be completely depleted, so as to obtain low conductivity. On-resistance, and maintain a high off-breakdown voltage. However, the device size can also be reduced to make the device area smaller, thereby reducing the on-resistanc...

AI Technical Summary

Problems solved by technology

On the basis of this structure, the on-resistance between the source terminal and the drain terminal of the LDMOS device will be very large, which will reduce the performance of the LDMOS device and affect the application prospect of the LDMOS device.

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