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High-speed SPI master-slave communication method, terminal equipment and storage medium

A communication method, SPI bus technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve problems such as misalignment, and achieve the effect of ensuring synchronization

Active Publication Date: 2020-10-02
明见(厦门)技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The present invention aims to provide a high-speed SPI master-slave communication method, terminal equipment and storage medium to solve the misalignment problem generated in high-speed SPI master-slave communication

Method used

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  • High-speed SPI master-slave communication method, terminal equipment and storage medium
  • High-speed SPI master-slave communication method, terminal equipment and storage medium
  • High-speed SPI master-slave communication method, terminal equipment and storage medium

Examples

Experimental program
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Embodiment 1

[0024] Such as Figure 1-4 As shown, according to an aspect of the present invention, a kind of high-speed SPI master-slave communication method is provided, and it may comprise the following steps:

[0025] S1: Connect the master and slave through the five-wire SPI bus, which is based on the existing four-wire (chip select signal line CS (Chip select), clock signal line SCLK (Serial Clock), master output / slave Machine input signal line MOSI (Master Output Slave Input) and master input / slave output signal line MISO (Master Input SlaveOutput)) type SPI bus is formed by adding a synchronous signal line SYNC, such as figure 1 shown. The synchronization signal line is connected to the GPIO of the host MCPU and the slave SCPPU, and a high level indicates that the slave SCPPU has data to send. Through the synchronous signal SYNC, the host MCPU can be notified, and the data exchange time between the MCPU and the SCPPU can be synchronized.

[0026] S2: Restrict the use of block com...

Embodiment 2

[0037] It may include a memory, a processor, and a computer program stored in the memory and operable on the processor, wherein the processor implements the steps in the above method embodiments when executing the computer program, for example, the embodiment 1, steps 1-7 and other method steps, or when the processor executes the computer program, the functions of the modules / units in the above device embodiments are realized.

[0038] Exemplarily, the computer program can be divided into one or more modules / units, and the one or more modules / units are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units may be a series of computer program instruction segments capable of accomplishing specific functions, and the instruction segments are used to describe the execution process of the computer program in the terminal device.

[0039] The terminal device may be a computing device such as a desktop computer, a notebook,...

Embodiment 3

[0043] The present invention also provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, wherein, when the computer program is executed by a processor, the steps of the above-mentioned method are implemented, for example, in Embodiment 1 Steps 1-7 and other method steps.

[0044] Each module / unit of a computer program may be stored in a computer-readable storage medium if it is realized in the form of a software functional unit and sold or used as an independent product. Based on this understanding, the present invention realizes all or part of the processes in the methods of the above embodiments, and can also be completed by instructing related hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer When the program is executed by the processor, the steps in the above-mentioned various method embodiments can be realized. Wherein, the computer program...

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Abstract

The invention relates to a high-speed SPI master-slave communication method, terminal equipment and a storage medium, and the method comprises the following steps: S1, enabling a master to be connected with a slave through a five-wire SPI bus; S2, limiting that a block communication form is adopted between a master and a slave, wherein each block data comprises an information header identifier ofa fixed byte and effective information data; S3, sending and receiving slave data, and setting a synchronization signal to be at a high level when the slave sends the data; and S4, sending and receiving host data, wherein the host detects a synchronization signal at regular time, when the synchronization signal is detected to be at a high level, the host starts to read and send data, and when thehost finishes reading a block of data, DMA sending completion interruption and DMA receiving completion interruption are generated from an opportunity and a corresponding interruption processing program is carried out. According to the invention, the problem of dislocation generated in the existing high-speed SPI master-slave communication can be solved.

Description

technical field [0001] The invention relates to the field of SPI communication, in particular to a high-speed SPI master-slave communication method, terminal equipment and a storage medium. Background technique [0002] In embedded electronic devices, CPU communication between boards often uses serial ports, and the current highest stable speed of serial ports is 460800. The serial port rate is no longer enough for applications that require large amounts of data and high-speed communication. The speed of SPI is much higher than that of the serial port, but SPI needs to set the master and slave. If the master (MCPU) and slave (SCPU) are not well coordinated, it will often lead to misalignment, and the entire data will be directly garbled. If the MCPU reads 500 bytes at a time, and the DMA of the SCPU sends 200 bytes at a time, when the 200 bytes of the SCPU are sent, it needs to interrupt processing and continue to copy the data to the sending buffer. If the data is not pre...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28G06F13/42
CPCG06F13/28G06F13/4282G06F2213/0002
Inventor 任赋朱进阳许学泽林雅
Owner 明见(厦门)技术有限公司
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