A semiconductor package device

Abstract

The present application discloses a semiconductor packaging device, which belongs to the technical field of semiconductors. The semiconductor package device disclosed herein includes a package substrate, at least one first chip, a first package body, and a bent electrical connector. The main chip that needs to be interconnected with the first chip is arranged in the first package body, and the side of the first package body has an exposed first electrical connection structure electrically connected to the main chip; The exposed part of the first electrical connection structure is electrically connected to part of the pads of the first chip, the rest of the pads of the first chip are electrically connected to the package substrate, and the first package body, the first chip and the package substrate are stacked. Therefore, the lateral space is saved, the overall volume of the device formed by interconnecting the first chip and the first package body is reduced, and the integration degree and reliability of the semiconductor package device are improved.

Description

technical field [0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor package device. Background technique [0002] With the upgrading of electronic products, the functions of electronic products are increasingly required to be more diversified and the volume is more compact. Therefore, the stacking method of chips capable of realizing different functions needs to compress the stacked volume as much as possible. [0003] In the prior art, when 3D stacking is used to form a semiconductor package device, through-silicon via technology (TSV, Through Silicon Via) is usually used to punch a through hole on the stacked chips, and conductive The multiple chips and the substrate are interconnected; alternatively, the pads on the front surfaces of the multiple chips are exposed in a staggered stacking manner, and then the multiple chips and the packaging substrate are interconnected by wire bonding. [0004] However, t...

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Problems solved by technology

[0004] However, through-silicon via technology requires extremely high process precision and will reduce the yield rate of semiconductor packaging devices. However, the method of staggered stacking and wiring requires a large volume of chips after staggered stacking, which is not conducive to improving semiconductor packaging devices. The level of integration, and there is a problem that the wiring connection is not firm

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