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A semiconductor package device and chip interconnection method

A technology for packaging devices and semiconductors, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, and semiconductor/solid-state device components, etc. It can solve the problems of difficult to take into account the reliability of volume connection, weak bonding wire connection, and large size of the main chip. , to reduce the volume, improve the yield and reliability, and achieve the effect of firm connection

Active Publication Date: 2022-07-12
NANTONG TONGFU MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The inventors of the present application found in the long-term research process that in the existing semiconductor packaging devices, the structural strength of the main chip with through holes is relatively poor, while the volume occupied by the staggered main chips is relatively large, and the bonding The connection of the line is also relatively weak, and it is difficult to meet the requirements of small size and reliable connection

Method used

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  • A semiconductor package device and chip interconnection method
  • A semiconductor package device and chip interconnection method
  • A semiconductor package device and chip interconnection method

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Embodiment Construction

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0042] see figure 1 and figure 2 , figure 1 is a schematic cross-sectional structure diagram of an embodiment of the semiconductor package device of the present application, figure 2 Yes figure 1 In the schematic cross-sectional structure diagram of an embodiment of the first package element in FIG. 2 , the semiconductor package device 20 includes: a substrate 202 , a plurality of first package elements 10 and a conductive adhesiv...

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Abstract

The present application discloses a semiconductor packaging device and a chip interconnection method. The semiconductor packaging device includes: a substrate, a plurality of first packaging elements and conductive adhesive, wherein the plurality of first packaging elements are stacked on the substrate, and the first packaging The element includes at least one main chip and an electrical connection structure, the electrical connection structure is electrically connected to the pads on the functional surface of the main chip and has an exposed part located on the side of the first package element; the conductive adhesive is located on a plurality of first packages arranged in layers The side surfaces of the components are electrically connected to the electrical connection structures located on the side surfaces of the plurality of first package components and the substrate. In the above manner, the present application can reduce the space occupied by the main chip after being stacked and improve the reliability of the connection between the main chip and the substrate.

Description

technical field [0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor package device and a chip interconnection method. Background technique [0002] With the upgrading of electronic products, the functions of electronic products are increasingly required to be more diversified and the volume is more compact. Therefore, the stacking method of chips that can realize functions needs to compress the stacking volume as much as possible. [0003] In the prior art, a through hole is usually provided on the main chip after stacking in the semiconductor package device, and the through hole is filled with conductive material to realize interconnection between the main chips and the substrate; The main chips are staggered and stacked, and the upper main chip does not completely cover the lower main chip to expose the pads of the main chip. Bonding is provided between the pads of the main chip and between the pads of the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/16H01L21/48H01L21/56H01L21/768H01L23/31H01L23/367H01L23/48
CPCH01L25/16H01L23/3107H01L23/481H01L23/3672H01L21/4882H01L21/56H01L21/76898H01L2224/18
Inventor 李骏戴颖
Owner NANTONG TONGFU MICROELECTRONICS CO LTD