Array substrate and preparation method thereof and display device

A technology of array substrates and substrate substrates, which is applied in the fields of instruments, semiconductor devices, optics, etc., can solve the problems of high cost and complex process steps, reduce production costs, reduce the number of patterning processes, and improve the over-engraving of the active layer The effect of the erosion problem

Pending Publication Date: 2020-11-06
BOE TECH GRP CO LTD +1
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Problems solved by technology

The process steps of the patterning process are more complicated and the cost is higher. Therefore, how to reduce the number of patterning processes to reduce the p

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  • Array substrate and preparation method thereof and display device
  • Array substrate and preparation method thereof and display device
  • Array substrate and preparation method thereof and display device

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[0048] For ease of understanding, the technical solutions provided by some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the proposed technical solution, rather than all the embodiments. Based on some embodiments of the present disclosure, all other embodiments that can be obtained by those skilled in the art fall within the protection scope of the present disclosure.

[0049] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms such as the third person singular "comprises" and the present participle "comprising" are used It is interpreted as the meaning of openness and inclusion, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" example)" o...

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Abstract

The embodiment of the invention discloses an array substrate and a preparation method thereof, and a display device, relates to the technical field of display, and aims to prevent an active layer frombeing over-etched and reduce the process frequency and the manufacturing cost. The array substrate comprises an underlayer substrate, a light shading pattern, a buffer pattern, an active layer, a gate insulating layer, a first passivation layer and source and drain electrodes, wherein the orthographic projection of the buffer pattern on the underlayer substrate covers the orthographic projectionof the active layer on the underlayer substrate, the orthographic projection of the buffer pattern on the underlayer substrate is within the orthographic projection range of the light shading patternon the underlayer substrate, the area of the orthographic projection of the buffer pattern on the underlayer substrate is smaller than that of the orthographic projection of the light shading patternon the underlayer substrate, a first via hole, a second via hole and a third via hole are formed in the gate insulating layer and the first passivation layer, one of the source electrode and the drainelectrode is coupled with the active layer through the first via hole, and the other one is coupled with the active layer through the second via hole and is coupled with the light shading pattern through the third via hole. The array substrate is applied to the display device, so that the display device displays a picture.

Description

technical field [0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] At present, with the development of liquid crystal display technology, metal oxide thin film transistors (Thin Film Transistor, TFT for short), for example, Indium Gallium Zinc Oxide (IGZO for short) thin film transistors, have high carrier mobility rate, gradually attracting people's attention. [0003] In the related art, a patterning process is used to form multiple film layers of metal oxide thin film transistors. The process steps of the patterning process are relatively complicated and the cost is high. Therefore, how to reduce the number of patterning processes to reduce the process cost and material cost, and improve the productivity of metal oxide thin film transistors is one of the main issues in the current research field. Contents of the invention ...

Claims

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Application Information

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IPC IPC(8): G02F1/1362G02F1/1343H01L27/12
CPCG02F1/1362G02F1/136209G02F1/136227G02F1/134363H01L27/127H01L27/1214H01L29/78633H01L27/1248H01L27/1225H01L27/1237
Inventor 田茂坤黄中浩吴旭齐成军王骏刘丹
Owner BOE TECH GRP CO LTD
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