Lightweight convolutional neural network reconfigurable deployment method based on FPGA

Abstract

The invention provides a lightweight convolutional neural network reconfigurable deployment method based on an FPGA. During deployment, adaptation to FPGA platforms with different resource conditionsis realized by configuring parameters such as the column number of convolution windows and the number of output channels; before operation, adaptation to different network layers is realized by configuring convolution kernel sizes, pooling step sizes, input and output feature map sizes and input and output channel numbers of different convolution layers; and constructing an FPGA-based lightweightconvolutional neural network accelerator to realize network reconfigurable deployment, wherein the lightweight convolutional neural network accelerator comprises an off-chip DDR data interaction unit,an on-chip storage buffer processing unit, a computing engine and a central control unit. According to the method, different implementation schemes can be selected for deployment for different FPGA platforms, so that existing resources of the FPGA platforms are utilized to the maximum extent, the characteristics of high parallelism, high throughput rate and low power consumption of the FPGA platforms are brought into full play, and convolutional neural network reasoning acceleration is realized efficiently and quickly under the condition of relatively low power consumption.

Description

technical field [0001] The present invention relates to the technical field of artificial intelligence, and more specifically relates to an FPGA-based lightweight convolutional neural network reconfigurable deployment method. Background technique [0002] At present, because the CPU platform cannot provide enough computing power, the GPU has become the preferred neural network processing platform due to its powerful computing performance. However, the GPU consumes a lot of power, and it is difficult to deploy it on an embedded platform that requires high power consumption. The FPGA-based neural network reasoning accelerator has become a new research hotspot, and is expected to surpass the GPU platform in terms of computing speed and energy efficiency. [0003] The current FPGA deployment scheme for convolutional neural networks faces two challenges: First, the operating frequency of FPGA is usually 100-300MHz, which is much lower than that of CPU and GPU. Designs are diffi...

AI Technical Summary

Problems solved by technology

[0003]The current FPGA deployment scheme of convolutional neural network faces two challenges: First, the operating frequency of FPGA is usually 100-300MHz, which is much lower than that of CPU and GPU. At the same time, due to the limited on-chip resources of the FPGA, it is difficult to achieve high computing performance and energy efficiency only with a simple design

Secondly, due to the lack of development frameworks like Caffe and Tensorflow for developing FPGA-based applications, it is much more difficult to develop FPGA applications than CPU and GPU

Moreover, the computational and storage complexity of the neural network algorithm is very high, and it is an open problem to balance the model size and algorithm accuracy.

Large-scale networks are difficult to apply in application scenarios that have strict requirements on energy consumption and delay

Images