Method and circuit for reducing area of high-capacity NAND flash memory, storage medium and terminal

Abstract

The invention discloses a method and circuit for reducing the area of a high-capacity NAND flash memory, a storage medium and a terminal. Data of a sensitive amplifier is read, and then latching is carried out through respective data latches; the data is cached through a data output buffer capable of supporting three states; due to the fact that three states can be supported, output of the data output buffer can be connected together, data connecting lines transversely penetrating through the horizontal direction of the chip are sharply reduced, the area of the high-capacity NOR Flash chip isreduced, and meanwhile the cost of the chip at the wafer manufacturing end is reduced.

Description

technical field [0001] The invention relates to the field of circuit technology, in particular to a method for reducing the area of ​​a high-capacity non-type flash memory, a circuit, a storage medium and a terminal. Background technique [0002] In the process of NOR Flash chip design, the feasibility of packaging needs to be considered. The width-to-length ratio or aspect ratio of the chip wafer should generally not be greater than 2.5:1. figure 1 It is a layout diagram corresponding to the main modules of the serial NOR Flash chip with a storage capacity of 64Mbit, 32Mbit, 16Mbit and 8Mbit. [0003] From figure 1 It can be seen that when the storage capacity of the serial NOR Flash is less than or equal to 64Mbit, the serial NOR Flash with a capacity below 64Mbit can use the same architecture, and the aspect ratio and aspect ratio of the chip wafer are both less than 2.5:1, satisfying encapsulation requirements. [0004] However, serial NOR Flash with a storage capacit...

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Problems solved by technology

[0005] Because the width of each 8Mbit memory block is longer (65nm process is about 1350um), if figure 2 If the left storage block (8Mbit-0 ~ 8Mbit-7) and the right storage block (8Mbit-8 ~ 8Mbit-15) reuse the same sense amplifier, for the leftmost storage unit and the rightmost storage unit, The metal traces connecting the storage unit to the sense amplifier are very different, and the difference is expected to be 3000um (such as image 3 As shown in the schematic diagram), this will cause a large difference in the characteristics of the leftmost and rightmost memory cells during the data reading process, and may even cause data reading errors when the clock frequency is high

[0006] Because the peripheral digital logic circuit needs to take the data from the data latch and output it to the IO pin of the chip after processing, the data latch can be multiplexed with the left and right sense amplifiers, but the left and right sense amplifiers and data latches need to be added Take the 128 sensitive amplifiers on the left and right as an example for the data connection between them. The 128 sensitive amplifiers on the left and right correspond to 128 data latches, and the 128 sensitive amplifiers on the left and right respectively cross the chip to the 128 data latches. There are a total of 256 data connections in the horizontal direction (128x2, please refer to Figure 4 Schematic diagram), on the 65nm NOR Flash process node, the routing channels occupied by these traces are about 66um, accounting for about 2.2% of the chip area of ​​65nm 128Mbit serial NOR Flash, increasing the chip area of ​​128Mbit serial NOR Flash by 2.2%. Directly increase the cost of chips at the wafer manufacturing end

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