3D memory device, memory structure thereof and memory structure control method

Abstract

The present application discloses a 3D memory device, a memory structure thereof, and a memory structure control method. The memory structure comprises a plurality of transistors connected in series between a first end and a second end, the plurality of transistors comprising: a first selection transistor, a gate of which is connected to a top selection gate line; a second selection transistor having a gate connected to the bottom selection gate line; and at least one memory transistor connected in series between the first selection transistor and the second selection transistor. The grid electrode of each storage transistor is connected with the corresponding word line. The first end of the storage structure is used for being connected to a first bit line, the second end of the storage structure is used for being connected to a second bit line, the first bit line and the second bit line are used for providing carriers with the same electrical property for channels of all transistors under programming and / or erasing operation, and therefore the programming and erasing speed is greatly increased.

Description

technical field [0001] The present invention relates to memory technology, and more specifically, to a 3D memory device, its storage structure, and a control method for the storage structure. Background technique [0002] The development direction of semiconductor technology is the reduction of feature size and the improvement of integration. For storage devices, the improvement of the storage density of the storage device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. [0003] In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. The 3D storage device includes a plurality of storage units stacked along the vertical direction, the integration degree can be doubled on a unit area wafer, and the cost ...

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Problems solved by technology

[0005] The object of the present invention is to provide an improved 3D memory device and its storage structure and the control method of the storage structure, by canceling the common source structure of the array, and adopting double bit lines to supply the respective transistors under programming and / or erasing operations respectively. The channel provides the same electrical charge carriers, which not only improves the noise problem, but also speeds up the programming and / or erasing of the device

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