3D dual fin channel dual-bar multi-functional field effect transistor and its making method

Abstract

The invention provides a three-dimensional double fin type channel dual-grid multifunctional field effect transistor and preparing method. The flied effect transistor is based on double SOI underlay,the cross sections of up and down two-layer silicon film channel are provided with two same rectangular fins separately, the upper double fin type channel aligns the lower double fin type channel andthe width is the same; the outboard of every double fin type channel is the grid oxygen and the common front grid, the inboard is the tunnel oxide layer, the silicon nitride trap layer, the barrier oxide layer and the common back grip and the inboard forms the dual-grip structure; two edges of the upper double fin type channel are connected with the upper, common n+ source and n+ leakage, two edges of the lower double fin type channel are connected with the lower, common p+ source and p+ leakage; the self- aligning front grip and back grip cover less with the up and down two-layer source and leakage; the upper n+ source and the lower p+ source are connected with the different electrodes, the upper n+ leakage and the lower p+ leakage are connected with the same electrode. The invention is provided with high-effective nMOSFET, pMOSFET and CMOS logical device function.

Description

technical field [0001] The invention belongs to the technical field of metal oxide semiconductor field effect transistor (MetalOxide Semiconductor Field Effect Transistor-MOSFET) in ultra-large scale integrated circuit (ULSI), in particular to a three-dimensional double fin type channel double gate multifunctional field effect transistor and its Preparation. Background technique [0002] With the wide application and high-speed development of VLSI, based on MOSFET, System On Chip (SOC) technology has aroused people's great interest more and more. The system chip is to integrate the whole system on one or as few integrated circuit chips as possible, and each chip can integrate two or more functions from the original single function. SOC technology can overcome various problems in board-level integration of multi-chips (such as delay between chips, reliability of printed circuit boards), and has outstanding advantages in improving system performance, reducing power consumptio...

AI Technical Summary

Problems solved by technology

[0006] However, the SOONO structure MOSFET multifunctional device shown in Document 1 is based on a planar double-gate device, and has the following problems: (1) The back gate ONO stack structure is too thick due to the device structure and manufacturing process (respectively 1.4nm, 42nm, 1.4nm, the total thickness reaches about 45nm), which makes the threshold window small (2.5V), the back gate voltage during programming / erasing is higher (up to 6V / -4V), and the programming / erasing time is longer (up to 0.5 ms / 0.5ms), the application of a thin tunnel oxide layer (1.4nm) makes the retention characteristics worse, and the too thick silicon nitride trap layer makes the redistribution of injected charges affect the reliability of the device; (2) the back gate is completely Covering the channel and source and drain, the band tunneling hot holes during erasing will be injected into the covered area of ​​the back gate and drain, affecting the DC characteristics and reliability of the device

[0007] At the same time, the SOONO structure MOSFET multifunctional device shown in Document 1 is based on a planar double-gate device, and its integration density still needs to be further improved; will also be restricted in

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